{"title":"智能功率SOI技术中后门效应对双极结晶体管的影响","authors":"S. Schwantes, M. Graf, V. Dudek","doi":"10.1109/ISPSD.2005.1487962","DOIUrl":null,"url":null,"abstract":"This work investigates the effect of the back gate electrode on bipolar junction transistors (BJTs) in smart power SOI technologies. The impact on the BJT is discussed by means of measurements and device simulations. It is shown that proper back gate biasing results in a significant performance improvement for either the NPN or the PNP transistor. A design strategy is presented that offers an optimized utilization of the back gate effect.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies\",\"authors\":\"S. Schwantes, M. Graf, V. Dudek\",\"doi\":\"10.1109/ISPSD.2005.1487962\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work investigates the effect of the back gate electrode on bipolar junction transistors (BJTs) in smart power SOI technologies. The impact on the BJT is discussed by means of measurements and device simulations. It is shown that proper back gate biasing results in a significant performance improvement for either the NPN or the PNP transistor. A design strategy is presented that offers an optimized utilization of the back gate effect.\",\"PeriodicalId\":154808,\"journal\":{\"name\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"volume\":\"110 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2005.1487962\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies
This work investigates the effect of the back gate electrode on bipolar junction transistors (BJTs) in smart power SOI technologies. The impact on the BJT is discussed by means of measurements and device simulations. It is shown that proper back gate biasing results in a significant performance improvement for either the NPN or the PNP transistor. A design strategy is presented that offers an optimized utilization of the back gate effect.