带有NVDMOS和rerefpldmos的PDP扫描驱动程序

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1487973

Zhilin Sun, Weifeng Sun, Y. Yi, Chang Chen, W. Yao, Zhenxiong Peng, Longxing Shi

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引用次数: 7

摘要

在1.2/spl μ m标准CMOS工艺基础上，开发了一种采用25/spl μ m厚外延的高压CMOS集成电路技术。在该技术中，LDMOS和VDMOS一起制作。结隔离用于将VDMOS与LDMOS、低压CMOS和其他VDMOS隔离开来。测试结果表明，输出级的上升时间约为45ns，下降时间约为50ns。由于技术简单，节省了成本。

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PDP scan driver with NVDMOS and RESURF PLDMOS

A high voltage CMOS IC technology by using 25/spl mu/m thick epitaxy based on 1.2/spl mu/m standard CMOS process has been developed. In this technology, LDMOS and VDMOS are fabricated together. Junction isolation is used to isolate VDMOS from LDMOS, low voltage CMOS, and other VDMOSs. Test results show that the rise time and the fall time of the output stage is about 45ns and 50ns, respectively. For the simplicity of the technology, the cost is saved.

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来源期刊

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

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