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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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Multi Chip Module with Minimum Parasitic Inductance for New Generation Voltage Regulator 新一代稳压器的最小寄生电感多芯片模块
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488028
Y. Kawaguchi, T. Kawano, H. Takei, S. Ono, A. Nakagawa
{"title":"Multi Chip Module with Minimum Parasitic Inductance for New Generation Voltage Regulator","authors":"Y. Kawaguchi, T. Kawano, H. Takei, S. Ono, A. Nakagawa","doi":"10.1109/ISPSD.2005.1488028","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488028","url":null,"abstract":"This paper analyzes the effects of parasitic inductances over the conversion efficiency of DC-DC converters by using Spice simulator. It was found that the self-turn-on of the low side MOSFET is triggered by large body diode reverse recovery current. A new multi chip module (MCM) has been developed in order to suppress the self-turn-on of the LS MOSFETs and to reduce the parasitic inductances. The MCM also has unique upper surface cooling feature. The MCMs successfully improve the conversion efficiency by using the MOSFETs with reduced body diode reverse recovery. Conversion efficiency can be further improved by reducing the gate resistance and optimizing the dead time","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"124 28","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120824262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Thermal protection of an 80V silicon-on-insulator LDMOS transistor for power-over-Ethernet applications 用于以太网供电应用的80V绝缘体上硅LDMOS晶体管的热保护
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487970
A. Hastings, S. Maramreddy, M. Patoka
{"title":"Thermal protection of an 80V silicon-on-insulator LDMOS transistor for power-over-Ethernet applications","authors":"A. Hastings, S. Maramreddy, M. Patoka","doi":"10.1109/ISPSD.2005.1487970","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487970","url":null,"abstract":"This paper describes thermal protection for the pass transistor of a power-over-Ethernet powered device controller developed on a bonded-wafer silicon-on-insulator process. The 1/spl Omega/, 80V LDMOS transistor dissipates up to 8W during a typical fault condition. Current limiting, tightly coupled over-temperature sensing, and drain-to-source voltage sensing combine to limit measured peak junction temperatures to less than 250/spl deg/C.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS compatible super junction LDMOST with N-buffer layer 具有n -缓冲层的CMOS兼容超级结LDMOST
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487976
I. Park, C. Salama
{"title":"CMOS compatible super junction LDMOST with N-buffer layer","authors":"I. Park, C. Salama","doi":"10.1109/ISPSD.2005.1487976","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487976","url":null,"abstract":"A CMOS compatible super junction LDMOST (SJ-LDMOST) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and the P-substrate to achieve charge compensation between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on resistance, excellent gate charge characteristics and reduced sensitivity to doping imbalance in the pillars.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132294638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
4kV 4H-SiC Epitaxial Emitter Bipolar Junction Transistors 4kV 4H-SiC外延发射极双极结晶体管
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488008
S. Balachandran, T. Chow, A. Agarwal, C. Scozzie, K. Jones
{"title":"4kV 4H-SiC Epitaxial Emitter Bipolar Junction Transistors","authors":"S. Balachandran, T. Chow, A. Agarwal, C. Scozzie, K. Jones","doi":"10.1109/ISPSD.2005.1488008","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488008","url":null,"abstract":"In this paper we present 4H-SiC BJTs with open-base blocking voltage (BVCEO) of 4000V (the upper limit for 4H-SiC BJT operation), specific on-resistance (Ron,sp)of 56 mOmega-cm 2, and common-emitter current gain beta ~ 9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128070627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Influence of buffer structures on static and dynamic ruggedness of high voltage FWDs 缓冲结构对高压FWDs静态和动态坚固性的影响
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487989
B. Heinze, H. Felsl, A. Mauder, H. Schulze, J. Lutz
{"title":"Influence of buffer structures on static and dynamic ruggedness of high voltage FWDs","authors":"B. Heinze, H. Felsl, A. Mauder, H. Schulze, J. Lutz","doi":"10.1109/ISPSD.2005.1487989","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487989","url":null,"abstract":"It is required to design free wheeling diodes (FWDs) to be robust against static and dynamic avalanche. Therefore we investigate the effect of different buffer structures and the influence of various bulk parameters. By numerical device simulation the effect of the buffer doping, base doping and base width on the static and dynamic behaviour of FWDs is analysed. We show the promising features of well designed buffers for ruggedness and their coherences to the static reverse characteristics.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131727534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Modeling substrate currents in smart power ICs 智能功率集成电路中衬底电流的建模
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487967
J. Oehmen, M. Olbrich, E. Barke
{"title":"Modeling substrate currents in smart power ICs","authors":"J. Oehmen, M. Olbrich, E. Barke","doi":"10.1109/ISPSD.2005.1487967","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487967","url":null,"abstract":"Switchings of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. We present a parasitic transistor model for post layout simulation, which accounts for a strongly in homogeneous current flow, a base width of up to a few hundred /spl mu/m, multiple base contacts and collectors, and whose parameters are easily extractable from layout and technology data.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123267811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High current operation of GaN power HEMT GaN功率HEMT的大电流工作
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488013
H. Ueda, M. Sugimoto, T. Uesugi, O. Fujishima, T. Kachi
{"title":"High current operation of GaN power HEMT","authors":"H. Ueda, M. Sugimoto, T. Uesugi, O. Fujishima, T. Kachi","doi":"10.1109/ISPSD.2005.1488013","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488013","url":null,"abstract":"We report high current operation of GaN power HEMTs fabricated on a sapphire substrate by metalorganic chemical vapor deposition (MOCVD). In order to decrease an electrical resistance of the wiring to take out a high current, the thickness of Al plating was 3 Pm. In addition, in order to decrease a thermal resistance, the substrate was ground to 150 Pm. The drain current was over 30 A and the specific on-resistance was 14.5 m: -cm 2 under pulse measurement with the gate width of 157 mm. A high temperature operation over 300 °C was also verified.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126143466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low loss and small SiP for DC-DC converters 低损耗，小SiP用于DC-DC转换器
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487979
M. Shiraishi, T. Iwasaki, N. Akiyama, T. Kawashima, N. Matsuura, S. Chiba
{"title":"Low loss and small SiP for DC-DC converters","authors":"M. Shiraishi, T. Iwasaki, N. Akiyama, T. Kawashima, N. Matsuura, S. Chiba","doi":"10.1109/ISPSD.2005.1487979","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487979","url":null,"abstract":"This paper presents a SiP (system in package) that integrates high-side and low-side MOSFETs and a driver IC. The developed SiP has been realized the smallest mount area and lowest loss of DC-DC converter compared with the conventional devices that have ever been reported. Low-inductance packaging technology and optimization of the MOSFETs and driver IC by the MCM method (MCM: mixed simulation of circuit and MOS-power-devices), reduce the mount area by 60% smaller and reduce the loss by 25% compared with conventional discrete devices, when Vin=12 V, Vout=1.3 V, Iout=25 A, f=1 MHz.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
1.5kV Novel 4H-SiC Lateral Channel (LC) JBS Rectifiers with Low Leakage Current and Capacitance 具有低漏电流和电容的1.5kV新型4H-SiC横向通道(LC) JBS整流器
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488006
Lin Zhu, Canhua Li, T. Chow, I. Bhat, K. Jones, C. Scozzie, A. Agarwal
{"title":"1.5kV Novel 4H-SiC Lateral Channel (LC) JBS Rectifiers with Low Leakage Current and Capacitance","authors":"Lin Zhu, Canhua Li, T. Chow, I. Bhat, K. Jones, C. Scozzie, A. Agarwal","doi":"10.1109/ISPSD.2005.1488006","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488006","url":null,"abstract":"We propose and experimentally demonstrate a novel 1.5kV JBS rectifier structure called LC-JBS rectifier that offers a lower reverse leakage current and faster switching speed. Test devices were fabricated using an epi regrowth technology over implanted p+ buried layer. We have obtained performance trade-offs between forward drop (<1.8V) with reverse leakage characteristics approaching that of PiN rectifiers, together with ~50% reduction of junction capacitance for LC-JBS rectifiers when compared to conventional Schottky rectifiers","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128060402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dedicated computation engine for power electronics application - a new architecture microcontroller 电力电子应用专用计算引擎——一种新型体系结构微控制器
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487940
T. Takahashi
{"title":"Dedicated computation engine for power electronics application - a new architecture microcontroller","authors":"T. Takahashi","doi":"10.1109/ISPSD.2005.1487940","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487940","url":null,"abstract":"Motor control is one of the most computationally demanding applications required for microcontroller. In order to satisfy the performance demand on motor control application, microcontroller or DSP manufacturers have traditionally been introducing higher MIPS performance together with memory size increase. The recent emerging appliance motor control such as variable speed motor controlled air conditioner and washer requires further advancement for energy saving which mandates the use of high energy efficiency motor such as permanent magnet motor even without a position sensor. It becomes difficult to fulfil this daunting task by using traditional computation method. This paper discusses a new architecture for motion control application based on a dedicated hardware computation engine. This paper goes through technical comparison between traditional DSP/microcontroller based solution and this new solution for emerging appliance motor control and discusses the silicon architecture advancement.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128303674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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