Modeling substrate currents in smart power ICs

Abstract

Switchings of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. We present a parasitic transistor model for post layout simulation, which accounts for a strongly in homogeneous current flow, a base width of up to a few hundred /spl mu/m, multiple base contacts and collectors, and whose parameters are easily extractable from layout and technology data.