低损耗，小SiP用于DC-DC转换器

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1487979

M. Shiraishi, T. Iwasaki, N. Akiyama, T. Kawashima, N. Matsuura, S. Chiba

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引用次数: 20

摘要

本文提出了一种集成高侧、低侧mosfet和驱动IC的系统级封装(system in package, SiP)，与已有的传统器件相比，实现了最小的安装面积和最低的DC-DC变换器损耗。当Vin=12 V, Vout=1.3 V, Iout=25 A, f=1 MHz时，采用MCM方法对mosfet和驱动IC进行低电感封装技术和优化(MCM:混合模拟电路和mos功率器件)，与传统分立器件相比，封装面积减小60%，损耗降低25%。

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Low loss and small SiP for DC-DC converters

This paper presents a SiP (system in package) that integrates high-side and low-side MOSFETs and a driver IC. The developed SiP has been realized the smallest mount area and lowest loss of DC-DC converter compared with the conventional devices that have ever been reported. Low-inductance packaging technology and optimization of the MOSFETs and driver IC by the MCM method (MCM: mixed simulation of circuit and MOS-power-devices), reduce the mount area by 60% smaller and reduce the loss by 25% compared with conventional discrete devices, when Vin=12 V, Vout=1.3 V, Iout=25 A, f=1 MHz.

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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

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