{"title":"具有n -缓冲层的CMOS兼容超级结LDMOST","authors":"I. Park, C. Salama","doi":"10.1109/ISPSD.2005.1487976","DOIUrl":null,"url":null,"abstract":"A CMOS compatible super junction LDMOST (SJ-LDMOST) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and the P-substrate to achieve charge compensation between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on resistance, excellent gate charge characteristics and reduced sensitivity to doping imbalance in the pillars.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"CMOS compatible super junction LDMOST with N-buffer layer\",\"authors\":\"I. Park, C. Salama\",\"doi\":\"10.1109/ISPSD.2005.1487976\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS compatible super junction LDMOST (SJ-LDMOST) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and the P-substrate to achieve charge compensation between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on resistance, excellent gate charge characteristics and reduced sensitivity to doping imbalance in the pillars.\",\"PeriodicalId\":154808,\"journal\":{\"name\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2005.1487976\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487976","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS compatible super junction LDMOST with N-buffer layer
A CMOS compatible super junction LDMOST (SJ-LDMOST) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and the P-substrate to achieve charge compensation between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on resistance, excellent gate charge characteristics and reduced sensitivity to doping imbalance in the pillars.