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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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Evaluation of self-heating effects on an innovative SOI technology ("Venezia" process) 创新SOI工艺(“Venezia”工艺)的自热效果评价
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487951
P. Villani, S. Favilla, L. Labate, E. Novarini, A. Ponza, R. Stella
{"title":"Evaluation of self-heating effects on an innovative SOI technology (\"Venezia\" process)","authors":"P. Villani, S. Favilla, L. Labate, E. Novarini, A. Ponza, R. Stella","doi":"10.1109/ISPSD.2005.1487951","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487951","url":null,"abstract":"In this paper we investigate the thermal resistance associated to a power DMOS device realized by means of an innovative SOI process (Venezia process). First we present a simple experimental technique enabling to characterize device thermal transient by looking at its related drain current waveform, then we analyze and discuss the obtained experimental results pointing out the difference in thermal resistance between Venezia buried oxide and the one manufactured by standard technology.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127238435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of fine surface chemical-mechanical polishing on the manufacturing yield of 1200V SiC Schottky barrier diodes 精细表面化学机械抛光对1200V SiC肖特基势垒二极管成品率的影响
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487995
D. Tournier, A. Pérez‐Tomás, P. Godignon, J. Millán, H. Mank, D. Turover, D. Hinchley, J. Rhodes
{"title":"Impact of fine surface chemical-mechanical polishing on the manufacturing yield of 1200V SiC Schottky barrier diodes","authors":"D. Tournier, A. Pérez‐Tomás, P. Godignon, J. Millán, H. Mank, D. Turover, D. Hinchley, J. Rhodes","doi":"10.1109/ISPSD.2005.1487995","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487995","url":null,"abstract":"Unlike other techniques for surface cleaning/etching such as dry etching (RIE, ICP), the new polishing process does not degrade Schottky diode forward characteristics. Thus, apart from the promising improvement of starting material quality, fine surface polishing seems to offer significant advantages in terms of increasing manufacturing yield.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127480684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel SOI lateral bipolar transistor with 30GHz f/sub max/ and 27V BV/sub CEO/ for RF power amplifier applications 一种新型SOI横向双极晶体管，具有30GHz f/sub max/和27V BV/sub CEO/，用于射频功率放大器应用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2006.1666049
I.-S.M. Sun, W. Ng, K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita, Y. Furukawa, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka
{"title":"A novel SOI lateral bipolar transistor with 30GHz f/sub max/ and 27V BV/sub CEO/ for RF power amplifier applications","authors":"I.-S.M. Sun, W. Ng, K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita, Y. Furukawa, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka","doi":"10.1109/ISPSD.2006.1666049","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666049","url":null,"abstract":"This paper describes a lateral bipolar transistor build on SOI substrate (ie. SOI-LBJT) for RF power amplifier applications. The lateral design concept significantly reduces parasitic resistances and capacitances, and enables very high operating frequency and good trade-off to breakdown voltages. This concept is validated by fabricated SOI-LBJT, which delivers frequency (f/sub t//f/sub max/ = 12/30GHz) and breakdown voltage (BV/sub CEO/=27 V) that approaches the Johnson's limit. This is the first reported Si-BJT that reaches Johnson's limit with BV/sub CEO/ above 10V.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117180642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Architecture optimization of an N-channel LDMOS device dedicated to RF-power application 射频功率专用n通道LDMOS器件的结构优化
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487975
D. Muller, A. Giry, D. Pache, J. Mourier, B. Szelag, A. Monroy
{"title":"Architecture optimization of an N-channel LDMOS device dedicated to RF-power application","authors":"D. Muller, A. Giry, D. Pache, J. Mourier, B. Szelag, A. Monroy","doi":"10.1109/ISPSD.2005.1487975","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487975","url":null,"abstract":"The improvement of the dynamic performances of a RF LDMOS power amplifier (PA) is presented via the investigation of two device architectures differently optimized: LDMOSo1 and LDMOSo2. The diminution of the capacitance Cds was achieved on LDMOSo1. The reduction of key parameters such as the gate resistance Rg, and the capacitance Cgd was obtained on LDMOSo2. Both optimized architectures could be combined to gain on dynamic performances and complete the LDMOSFET optimization.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131108669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Above 500V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth 采用深沟槽刻蚀和外延生长制备500V以上级超结mosfet
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487943
S. Iwamoto, K. Takahashi, H. Kuribayashi, S. Wakimoto, K. Mochizuki, H. Nakazawa
{"title":"Above 500V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth","authors":"S. Iwamoto, K. Takahashi, H. Kuribayashi, S. Wakimoto, K. Mochizuki, H. Nakazawa","doi":"10.1109/ISPSD.2005.1487943","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487943","url":null,"abstract":"Above 500V class superjunction (SJ) MOSFETs fabricated by deep-trench etching and epitaxial growth are investigated. These SJ-MOSFETs show the lowest specific on-resistance (RonA) of 21.3mOmegacm2 at a breakdown voltage (VB) of 540V, among reported trench-filling type of devices in the same voltage class. These RonA-VB trade-off characteristics are accomplished by optimizing doping concentrations of n- and p- column regions. In addition, low reverse biased leakage current has been achieved by filling deep trenches with defect-free single crystal silicon","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125647661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Switching loss optimization of 20V devices integrated in a 0.13 μm CMOS technology for portable applications 集成在0.13 μm CMOS技术中的20V器件的开关损耗优化，用于便携式应用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488020
C. Grelu, N. Baboux, R. Bianchi, C. Plossu
{"title":"Switching loss optimization of 20V devices integrated in a 0.13 μm CMOS technology for portable applications","authors":"C. Grelu, N. Baboux, R. Bianchi, C. Plossu","doi":"10.1109/ISPSD.2005.1488020","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488020","url":null,"abstract":"Switching performances of low-cost 20V drift-MOSFETs and diffused-MOSFETs power devices are compared. Thanks to a new dynamic gate capacitance measurement protocol, the average gate capacitance responsible for power losses during fast switching transitions is estimated and the Miller effect contribution is quantified. Optimized drift-MOSFETs with reduced gate length and gate to drain overlap present comparable and even better performances than diffused-MOSFETs. Moreover they present the lowest process over-cost, making them excellent and very competitive candidates for low-cost portable power management applications","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132332754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A new combined local and lateral design technique for increased SOA of large area IGCTs 一种新的局部和横向结合设计技术，用于提高大面积igct的SOA
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487986
T. Stiasny, P. Streit
{"title":"A new combined local and lateral design technique for increased SOA of large area IGCTs","authors":"T. Stiasny, P. Streit","doi":"10.1109/ISPSD.2005.1487986","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487986","url":null,"abstract":"In this paper we present our newly developed IGCT design concept for increased SOA performance. The new technology consists of a combination of local and lateral design techniques for improved current distribution across large area devices, thereby realizing a new level of SOA capability for IGCT structures.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High performance power MOSFETs with strained-Si channel 具有应变硅沟道的高性能功率mosfet
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487983
Young‐Kyun Cho, S. Kwon, Hee-Bum Jung, Jongdae Kim
{"title":"High performance power MOSFETs with strained-Si channel","authors":"Young‐Kyun Cho, S. Kwon, Hee-Bum Jung, Jongdae Kim","doi":"10.1109/ISPSD.2005.1487983","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487983","url":null,"abstract":"To improve a current drivability and an on-resistance characteristic of the high voltage MOSFET, we propose a novel power MOSFET employing a strained-Si channel structure. A 20nm thick strained-Si low field channel NMOSFET with a 0.75/spl mu/m thick Si/sub 0.8/Ge/sub 0.2/ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with conventional Si channel high voltage NMOSFET, while suppressing breakdown voltage and subthreshold slope characteristic degradation by 6% and 8% respectively. Also, the strained-Si high voltage NMOSFET improved the transconductance by 28% and 52% at linear and saturation regime.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116463508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
20V Asymmetric Complementary Power Device Implementation within a 0.25um CMOS Technology for Power Management 采用0.25um CMOS技术实现20V非对称互补电源器件
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488027
T. Letavic, R. Cook, R. Brock, H. Effing, R. Einerhand
{"title":"20V Asymmetric Complementary Power Device Implementation within a 0.25um CMOS Technology for Power Management","authors":"T. Letavic, R. Cook, R. Brock, H. Effing, R. Einerhand","doi":"10.1109/ISPSD.2005.1488027","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488027","url":null,"abstract":"This paper presents a process flow in which a 20V-class of power devices is added to baseline 0.25mum CMOS technology by forming asymmetric extended-drain device structures in which shallow-trench-isolation (STI) is incorporated within the device unit cell, forming a gate extended-drain dielectric region. The Rsp-BVds figure-of-merit is consistent with best-in-class for this device construction (0.16 mOhm cm2/24V), and the isolated high-voltage diode capability make this process cost-effective for implementation of mobile power management circuit topologies, including multiple-output DC-DC converters, battery chargers, linear regulators, audio power amplifiers, and white-light backlighting systems","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130302633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Investigations on current filamentation of IGBTs under undamped inductive switching conditions 无阻尼电感开关条件下igbt电流丝化的研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487992
T. Shoji, M. Ishiko, T. Fukami, T. Ueta, K. Hamada
{"title":"Investigations on current filamentation of IGBTs under undamped inductive switching conditions","authors":"T. Shoji, M. Ishiko, T. Fukami, T. Ueta, K. Hamada","doi":"10.1109/ISPSD.2005.1487992","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487992","url":null,"abstract":"We have investigated current filamentation of IGBTs occurring under UIS (undamped inductive switching) conditions, by using electro-thermal device simulations. In this paper, we present that the formation of a current filament inevitably takes place even if the device active region include no weak spots. In addition, it is clarified that the current filament travels inside the active region with Joule self-heating, and the filament pinning due to parasitic bipolar action at the weak spot leads to lowering UIS capability.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125532470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
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