Architecture optimization of an N-channel LDMOS device dedicated to RF-power application

Abstract

The improvement of the dynamic performances of a RF LDMOS power amplifier (PA) is presented via the investigation of two device architectures differently optimized: LDMOSo1 and LDMOSo2. The diminution of the capacitance Cds was achieved on LDMOSo1. The reduction of key parameters such as the gate resistance Rg, and the capacitance Cgd was obtained on LDMOSo2. Both optimized architectures could be combined to gain on dynamic performances and complete the LDMOSFET optimization.