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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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Development of Repetitive Pulsed Power Generators Using Power Semiconductor Devices 利用功率半导体器件研制重复脉冲电源
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487941
Weihua Jiang, N. Oshima, T. Yokoo, K. Yatsui, K. Takayama, M. Wake, N. Shimizu, A. Tokuchi
{"title":"Development of Repetitive Pulsed Power Generators Using Power Semiconductor Devices","authors":"Weihua Jiang, N. Oshima, T. Yokoo, K. Yatsui, K. Takayama, M. Wake, N. Shimizu, A. Tokuchi","doi":"10.1109/ISPSD.2005.1487941","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487941","url":null,"abstract":"Power semiconductor devices have been used in development of various pulsed power generators for industrial applications. A repetitive pulsed high-voltage modulator using power MOSFETs has been developed for accelerator applications. It is capable of high-speed switching of 2kV at repetition rate of 1 MHz. This modulator, operating in continuous mode at average power level of 30 kW, has played an important role in the experimental demonstration of Induction Synchrotron. In the same time, SIThy is also tested for the same application since it has higher power capability than MOSFET. Initial experiments have demonstrated 1-MHz operation of SIThy at 2kV in burst mode. A pulsed high-voltage generator using SIThy has been developed for applications in flue-gas treatment. This generator uses a newly developed inductive-energy-storage circuit to achieve both output-voltage multiplication and pulse-width compression. It is very compact and it needs a 12-V (DC) battery as the only power supply to give output of 12 kV with pulse width of 100 ns at repetition rate of 2 kHz in continuous mode. A pulsed high-current modulator has been developed for extreme-ultraviolet generation. It uses IGBTs as the main switch and employs magnetic-pulse-compression to achieve pulsed high current. The output reaches 40 kA with pulse width of 240 ns while operating at repetition rate of 1 kHz in burst mode. This modulator is used in light source development for next-generation lithography. Semiconductor opening switches (SOS) are used in pulsed power generators for excimer laser pumping and flue-gas treatment. These developments are mostly international collaboration with Russian scientists, while efforts are being made to develop SOS devices in Japan.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126060336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Interaction between monolithically integrated JI-LIGBTs under clamped inductive switching 箝位电感开关下单片集成ji - lights之间的相互作用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487965
D. Green, S. Hardikar, M. Sweet, K. Vershinin, E. M. Sankara Narayanan
{"title":"Interaction between monolithically integrated JI-LIGBTs under clamped inductive switching","authors":"D. Green, S. Hardikar, M. Sweet, K. Vershinin, E. M. Sankara Narayanan","doi":"10.1109/ISPSD.2005.1487965","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487965","url":null,"abstract":"Due to the increasing demand for multi-functionality in power integrated circuits, consideration must be given as to how multiple, adjacent, monolithically integrated, high voltage lateral power devices interact with each other when operated independently of one another. For the first time, we demonstrate through extensive experiments and simulations that the breakdown, on-state, switching and safe operating area performance of LIGBT are all significantly affected by the operating conditions of an adjacent LIGBT in junction isolation technology.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125987454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process 沟槽垂直DMOS (VDMOS)功率晶体管的单片集成成BCD工艺
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487947
T. Dyer, J. McGinty, A. Strachan, C. Bulucea
{"title":"Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process","authors":"T. Dyer, J. McGinty, A. Strachan, C. Bulucea","doi":"10.1109/ISPSD.2005.1487947","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487947","url":null,"abstract":"The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved for the integrated trench VDMOS using a minimum feature size of 1 /spl mu/m.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125995593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Optimization of 5V power devices based on CMOS for hot-carrier degradation 基于CMOS的5V功率器件热载流子退化优化
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488019
K. Nakamura, T. Naka, K. Matsushita, T. Matsudai, N. Yasuhara, K. Endo, F. Suzuki, A. Nakagawa
{"title":"Optimization of 5V power devices based on CMOS for hot-carrier degradation","authors":"K. Nakamura, T. Naka, K. Matsushita, T. Matsudai, N. Yasuhara, K. Endo, F. Suzuki, A. Nakagawa","doi":"10.1109/ISPSD.2005.1488019","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488019","url":null,"abstract":"We propose “power CMOS,” suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m: mm 2 for NMOS and 21.1m: mm 2 for PMOS.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133410666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
HMS rectifier: a novel hybrid MOS Schottky diode concept with no barrier lowering, low leakage current and high breakdown voltage HMS整流器:一种新型的混合MOS肖特基二极管概念，无降垒，低漏电流和高击穿电压
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487948
V. Khemka, V. Parthasarathy, R. Zhu, A. Bose
{"title":"HMS rectifier: a novel hybrid MOS Schottky diode concept with no barrier lowering, low leakage current and high breakdown voltage","authors":"V. Khemka, V. Parthasarathy, R. Zhu, A. Bose","doi":"10.1109/ISPSD.2005.1487948","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487948","url":null,"abstract":"In this paper we propose and demonstrate a novel Schottky device concept, which is capable of achieving ultra low leakage current with high breakdown voltage. The proposed Schottky diode is conceived and designed with a lateral configuration for deep sub-micron smart power technologies but can also be designed in a vertical discrete configuration. A combination of depletion mode MOSFET and n or p-type Schottky junctions are utilized to create hybrid MOS Schottky (HMS) diode where the high reverse bias voltage is blocked by the MOSFET. The device is first demonstrated in a circuit configuration with discrete Schottky diode and a MOSFET. Subsequently, low separate monolithic integrated versions of the diode are proposed and realized. The integrated version of the diode achieved near-ideal characteristics with an ideality factor, n of 1.04 and a barrier height o/sub B/ of 0.64eV.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130487398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Progress in Technology CAD for Power Devices, Circuits and Systems 电力器件、电路和系统CAD技术进展
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487939
W. Fichtner, N. Braga, M. Ciappa, V. Mickevičius, M. Schenkel
{"title":"Progress in Technology CAD for Power Devices, Circuits and Systems","authors":"W. Fichtner, N. Braga, M. Ciappa, V. Mickevičius, M. Schenkel","doi":"10.1109/ISPSD.2005.1487939","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487939","url":null,"abstract":"Over the past decade, the utilization of technology CAD (TCAD) tools has become widespread in industry and academia. The enormous progress in computing hardware and software technology, together with significant advances in physical modelling accuracy, and speed and robustness of numerical algorithms, have made TCAD to a cost-effective albeit powerful technology that complements experimental approaches to wafer processing and metrology.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123899109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of E-field distributions within high-power devices using IBIC microscopy 用IBIC显微镜分析大功率器件内的电场分布
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487994
M. Zmeck, L. Balk, R. Heiderhoff, T. Osipowicz, F. Watt, J. Phang, A. Khambadkone, F. Niedernostheide, H. Schulze
{"title":"Analysis of E-field distributions within high-power devices using IBIC microscopy","authors":"M. Zmeck, L. Balk, R. Heiderhoff, T. Osipowicz, F. Watt, J. Phang, A. Khambadkone, F. Niedernostheide, H. Schulze","doi":"10.1109/ISPSD.2005.1487994","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487994","url":null,"abstract":"In this paper time resolved ion beam induced charge (IBIC) microscopy is introduced as a tool for the characterization of electrical field distributions within reverse biased high-power devices. Two dimensional maps of different parameters of the measured IBIC transients are discussed and compared with simulated IBIC data.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115966131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Thermal and electrical simulation of smart power circuits by network analysis 基于网络分析的智能电源电路热电仿真
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487968
J. Teichmann, W. Kraus, F. Liebermann, G. Taschner, C. Wallner
{"title":"Thermal and electrical simulation of smart power circuits by network analysis","authors":"J. Teichmann, W. Kraus, F. Liebermann, G. Taschner, C. Wallner","doi":"10.1109/ISPSD.2005.1487968","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487968","url":null,"abstract":"A Spectre-based method is described for complex electrical-thermal simulations of smart power circuits. The packaged circuit of a system is divided into numerous small columns. They form a large electrical representation of the thermal network. The electrical circuit sends the dissipated power to the thermal network and receives the temperature. All transistors of the system have individual temperatures. An EKV transistor model with temperature input and power output is used. Transient simulations and measurements are compared.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123490751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Ultra-low Von and High Voltage 4H-SiC Heterojunction Diode 超低Von和高压4H-SiC异质结二极管
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488007
H. Tanaka, T. Hayashi, Y. Shimoida, S. Yamagami, S. Tanimoto, M. Hoshi
{"title":"Ultra-low Von and High Voltage 4H-SiC Heterojunction Diode","authors":"H. Tanaka, T. Hayashi, Y. Shimoida, S. Yamagami, S. Tanimoto, M. Hoshi","doi":"10.1109/ISPSD.2005.1488007","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488007","url":null,"abstract":"We demonstrate a heterojunction diode (HJD) fabricated with p + -type polycrystalline silicon on an n - -type epitaxial layer of 4H-SiC. The HJD achieved extremely low Von and high reverse blocking voltage compared with a SiC Schottky barrier diode (SBD). The HJD shows good diode characteristics for temperatures ranging up to 200°C. Measured switching characteristics of the HJD exhibit almost zero reverse recovery similar to that of the SBD.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128553600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Evolution of the 1600 V, 20 A, SiC Bipolar Junction Transistors 1600v, 20a, SiC双极结晶体管的发展
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488003
A. Agarwal, S. Krishnaswami, J. Richmond, C. Capell, S. Ryu, J. Palmour, S. Balachandran, T. Chow, S. Bayne, B. Geil, C. Scozzie, K. Jones
{"title":"Evolution of the 1600 V, 20 A, SiC Bipolar Junction Transistors","authors":"A. Agarwal, S. Krishnaswami, J. Richmond, C. Capell, S. Ryu, J. Palmour, S. Balachandran, T. Chow, S. Bayne, B. Geil, C. Scozzie, K. Jones","doi":"10.1109/ISPSD.2005.1488003","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488003","url":null,"abstract":"SiC power BJTs have been developed over the last five years into a sufficiently mature technology (1-5). The reliability and applications of these devices are now being studied. This paper summarizes the evolution of this development culminating into the most recent performance of the 1600 V, 20 A devices with a current gain of 40 in the linear region, a forced current gain of 27 in the saturation region and a specific on-resistance of 4.5 mohm-cm 2 .","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128662859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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