{"title":"沟槽垂直DMOS (VDMOS)功率晶体管的单片集成成BCD工艺","authors":"T. Dyer, J. McGinty, A. Strachan, C. Bulucea","doi":"10.1109/ISPSD.2005.1487947","DOIUrl":null,"url":null,"abstract":"The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved for the integrated trench VDMOS using a minimum feature size of 1 /spl mu/m.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process\",\"authors\":\"T. Dyer, J. McGinty, A. Strachan, C. Bulucea\",\"doi\":\"10.1109/ISPSD.2005.1487947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved for the integrated trench VDMOS using a minimum feature size of 1 /spl mu/m.\",\"PeriodicalId\":154808,\"journal\":{\"name\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2005.1487947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process
The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved for the integrated trench VDMOS using a minimum feature size of 1 /spl mu/m.