K. Nakamura, T. Naka, K. Matsushita, T. Matsudai, N. Yasuhara, K. Endo, F. Suzuki, A. Nakagawa
{"title":"Optimization of 5V power devices based on CMOS for hot-carrier degradation","authors":"K. Nakamura, T. Naka, K. Matsushita, T. Matsudai, N. Yasuhara, K. Endo, F. Suzuki, A. Nakagawa","doi":"10.1109/ISPSD.2005.1488019","DOIUrl":null,"url":null,"abstract":"We propose “power CMOS,” suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m: mm 2 for NMOS and 21.1m: mm 2 for PMOS.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1488019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We propose “power CMOS,” suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m: mm 2 for NMOS and 21.1m: mm 2 for PMOS.