基于CMOS的5V功率器件热载流子退化优化

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1488019

K. Nakamura, T. Naka, K. Matsushita, T. Matsudai, N. Yasuhara, K. Endo, F. Suzuki, A. Nakagawa

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引用次数: 2

摘要

我们提出“功率CMOS”，适合作为大电流输出器件使用。该结构可采用低成本的0.6um逻辑CMOS工艺制造，即使在热电子应力下也能保证长期可靠性。所开发的功率CMOS实现了低比电阻，NMOS为8.1m: mm 2, PMOS为21m: mm 2。

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Optimization of 5V power devices based on CMOS for hot-carrier degradation

We propose “power CMOS,” suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m: mm 2 for NMOS and 21.1m: mm 2 for PMOS.

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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

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