集成在0.13 μm CMOS技术中的20V器件的开关损耗优化，用于便携式应用

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1488020

C. Grelu, N. Baboux, R. Bianchi, C. Plossu

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引用次数: 11

摘要

比较了低成本的20V漂移mosfet和扩散mosfet功率器件的开关性能。由于一种新的动态门电容测量协议，估计了在快速开关转换期间负责功率损耗的平均门电容，并量化了米勒效应的贡献。优化后的栅极长度和栅极漏极重叠减少的漂移mosfet表现出与扩散mosfet相当甚至更好的性能。此外，它们具有最低的工艺超支成本，使其成为低成本便携式电源管理应用的优秀且极具竞争力的候选产品

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Switching loss optimization of 20V devices integrated in a 0.13 μm CMOS technology for portable applications

Switching performances of low-cost 20V drift-MOSFETs and diffused-MOSFETs power devices are compared. Thanks to a new dynamic gate capacitance measurement protocol, the average gate capacitance responsible for power losses during fast switching transitions is estimated and the Miller effect contribution is quantified. Optimized drift-MOSFETs with reduced gate length and gate to drain overlap present comparable and even better performances than diffused-MOSFETs. Moreover they present the lowest process over-cost, making them excellent and very competitive candidates for low-cost portable power management applications

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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

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