1600V 4H-SiC UMOSFETs with dual buffer layers

Abstract

This paper presents the design and fabrication of 1600V 4H-SiC UMOSFETs with a novel dual buffer layer structure, which shortens the trench etching time by 2/spl times/ and achieves a high channel periphery density of 3330cm/cm/sup 2/ for low specific on-resistance. The device exhibits 50m/spl Omega/-cm/sup 2/ of specific on-resistance with /spl sim/1/spl mu/m of channel length, and could be further reduced with <1/spl mu/m channel length and optimal fabrication process.