具有双缓冲层的1600V 4H-SiC umosfet

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1487988

Q. Zhang, M. Gomez, C. Bui, E. Hanna

{"title":"具有双缓冲层的1600V 4H-SiC umosfet","authors":"Q. Zhang, M. Gomez, C. Bui, E. Hanna","doi":"10.1109/ISPSD.2005.1487988","DOIUrl":null,"url":null,"abstract":"This paper presents the design and fabrication of 1600V 4H-SiC UMOSFETs with a novel dual buffer layer structure, which shortens the trench etching time by 2/spl times/ and achieves a high channel periphery density of 3330cm/cm/sup 2/ for low specific on-resistance. The device exhibits 50m/spl Omega/-cm/sup 2/ of specific on-resistance with /spl sim/1/spl mu/m of channel length, and could be further reduced with <1/spl mu/m channel length and optimal fabrication process.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"141 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"1600V 4H-SiC UMOSFETs with dual buffer layers\",\"authors\":\"Q. Zhang, M. Gomez, C. Bui, E. Hanna\",\"doi\":\"10.1109/ISPSD.2005.1487988\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and fabrication of 1600V 4H-SiC UMOSFETs with a novel dual buffer layer structure, which shortens the trench etching time by 2/spl times/ and achieves a high channel periphery density of 3330cm/cm/sup 2/ for low specific on-resistance. The device exhibits 50m/spl Omega/-cm/sup 2/ of specific on-resistance with /spl sim/1/spl mu/m of channel length, and could be further reduced with <1/spl mu/m channel length and optimal fabrication process.\",\"PeriodicalId\":154808,\"journal\":{\"name\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"volume\":\"141 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2005.1487988\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487988","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 26

摘要

本文提出了一种新型双缓冲层结构的1600V 4H-SiC umosfet的设计和制造方法，该方法将沟槽刻蚀时间缩短了2/ 1倍，并在低比导通电阻的情况下实现了高达3330cm/cm/sup 2/的沟道外围密度。当通道长度为/spl sim/1/spl mu/m时，器件的比导通电阻为50m/spl Omega/-cm/sup / 2/;当通道长度小于1/spl mu/m时，器件的比导通电阻可进一步降低。

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1600V 4H-SiC UMOSFETs with dual buffer layers

This paper presents the design and fabrication of 1600V 4H-SiC UMOSFETs with a novel dual buffer layer structure, which shortens the trench etching time by 2/spl times/ and achieves a high channel periphery density of 3330cm/cm/sup 2/ for low specific on-resistance. The device exhibits 50m/spl Omega/-cm/sup 2/ of specific on-resistance with /spl sim/1/spl mu/m of channel length, and could be further reduced with <1/spl mu/m channel length and optimal fabrication process.

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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

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