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2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)最新文献

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Energy-efficient Annealing Process of HfO2-based Ferroelectric Capacitor using UV-LED for Green Manufacturing UV-LED绿色制造hfo2基铁电电容器的节能退火工艺
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103013
Hirotaka Yamada, Satoru Furue, Takehiko Yokomori, Yuki Itoya, T. Saraya, T. Hiramoto, M. Kobayashi
{"title":"Energy-efficient Annealing Process of HfO2-based Ferroelectric Capacitor using UV-LED for Green Manufacturing","authors":"Hirotaka Yamada, Satoru Furue, Takehiko Yokomori, Yuki Itoya, T. Saraya, T. Hiramoto, M. Kobayashi","doi":"10.1109/EDTM55494.2023.10103013","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103013","url":null,"abstract":"Crystallization of ferroelectric $text{Hf}_{0.5}text{Zr}_{0.5}mathrm{O}_{2}$ (HZO) capacitors with TiN electrodes is demonstrated using ultraviolet (UV)-LED annealing process, for the first time. The ferroelectric characteristics obtained by this method are comparable to those achieved by conventional infrared (IR)-RTA process at 400°C ~ 450°C. Since the absorptance of the ferroelectric films is highest in UV region, the UV-LED annealing process is promising to achieve much higher energy-efficient annealing process than the conventional IR-RTA method for green manufacturing.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122971944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Optimization of a Double Cladding Octo-wing Segmented Cladding Fibe Using Response Surface Methodology 基于响应面法的双包层八翼分段包层光纤设计与优化
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103129
M. Pournoury, Donghyun Kim
{"title":"Design and Optimization of a Double Cladding Octo-wing Segmented Cladding Fibe Using Response Surface Methodology","authors":"M. Pournoury, Donghyun Kim","doi":"10.1109/EDTM55494.2023.10103129","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103129","url":null,"abstract":"A double cladding octo-wing segmented cladding fiber (DC-OW-SCF) consists of a resonant layer with the characteristic of large mode area is proposed and optimized. Box-Behnken approach was used to numerically modeled thirteen different design cases by finite element method. To maximize the effective mode area (EMA) as an objective function, response surface methodology was applied. For the optimal DC-OW-SCF, the EMA as large as 706 $upmu mathrm{m}^{2}$ at the wavelength of 1.550 $upmu mathrm{m}$ was achieved. The optimized SCF can be used for high power fiber lasers and amplifiers.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications 神经形态应用中电荷捕获突触器件性能指标的优化
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103084
Md. Hasan Raza Ansari, Nazek El‐Atab
{"title":"Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications","authors":"Md. Hasan Raza Ansari, Nazek El‐Atab","doi":"10.1109/EDTM55494.2023.10103084","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103084","url":null,"abstract":"This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (~105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121264425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new back-to-back graded AlGaN barrier for complementary integration technique based on GaN/AlGaN/GaN platform 基于GaN/AlGaN/GaN平台互补集成技术的新型背靠背梯度AlGaN势垒
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103055
Jinggui Zhou, H. Do, M. M. De Souza
{"title":"A new back-to-back graded AlGaN barrier for complementary integration technique based on GaN/AlGaN/GaN platform","authors":"Jinggui Zhou, H. Do, M. M. De Souza","doi":"10.1109/EDTM55494.2023.10103055","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103055","url":null,"abstract":"A novel composite barrier layer with back-to-back graded AlGaN in a GaN/AlGaN/GaN epitaxial structure for high performance n- and p-channel devices on the same platform is proposed. By adjusting the relative thicknesses of the two graded layers, we obtain a spread in the width and concentration of carriers in the 3D slabs. The best barrier amongst those studied, enhances the on-current $(I_{ON})$ by 24.4% in low voltage n-channel devices, 32.2% the p-channel devices whereas the figure of merit of the power device is higher by 3 times, in comparison to the conventional platform.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116099916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application 存储器用双铁电栅极堆栈的嵌入式通道铁电栅极场效应晶体管的仿真
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103116
Simin Chen, D. Ahn, Seong Ui An, Younghyun Kim
{"title":"Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application","authors":"Simin Chen, D. Ahn, Seong Ui An, Younghyun Kim","doi":"10.1109/EDTM55494.2023.10103116","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103116","url":null,"abstract":"Over the years, there has been much research on ferroelectric field-effect transistors (FeFETs) for memory applications. In this work, we propose a novel recessed channel FeFET with gate metal-ferroelectric $(text{FE})-text{metal}-text{FE}-text{metal}-text{SiO}_{2}$ interlayer (IL)-silicon (MFMFMIS) gate stack, which is named a dual ferroelectric recessed channel FeFET (DF-RFeFET) aimed to increase the memory window (MW) for high-performance memory applications. With calibrated FE parameters and device models in technology computer-aided design (TCAD) simulation, we found that the DF-RFeFET can have a large MW of 3.2 V. In addition, guidelines for the DF-RFeFET design are provided in terms of the thickness ratio of the inner and outer FE layers to maximize the MW.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ML-assisted IC Test Binning with Real-Time Prediction at the Edge 基于边缘实时预测的ml辅助IC测试分箱
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10102972
Tomonori Honda, Thijs Haarhuis, J. D. David, Henri Hannink, Greg Prewitt, Vishnu Rajan
{"title":"ML-assisted IC Test Binning with Real-Time Prediction at the Edge","authors":"Tomonori Honda, Thijs Haarhuis, J. D. David, Henri Hannink, Greg Prewitt, Vishnu Rajan","doi":"10.1109/EDTM55494.2023.10102972","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10102972","url":null,"abstract":"IC Test is a critical part of semiconductor manufacturing and proper die binning and material disposition has an important impact on the overall yield and on the process monitoring and failure mode diagnostics. Edge analytics are becoming an increasingly important aspect of die disposition. By intercepting parts in real-time at the wafer test step, we can save downstream processing needs. In this paper we show how a machine learning model running on the ACS $text{Edge}^{text{TM}}$ infrastructure can provide 20-40x improvement in identification and binning of fail parts compared to conventional statistical screening methods. We also show that by incorporating known cost data, we can automatically guide users to optimally tune the model for maximal failure capture with minimal overkill and realize significant business savings.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125938440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GA Assisted ANN based GaN HEMT Model Development and Demonstration of its CAD Incorporation for Class-F Power Amplifier 基于遗传算法辅助神经网络的f类功率放大器GaN HEMT模型开发及其CAD集成论证
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10102998
S. Husain, G. Nauryzbayev, Mohammad S. Hashmi
{"title":"GA Assisted ANN based GaN HEMT Model Development and Demonstration of its CAD Incorporation for Class-F Power Amplifier","authors":"S. Husain, G. Nauryzbayev, Mohammad S. Hashmi","doi":"10.1109/EDTM55494.2023.10102998","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10102998","url":null,"abstract":"Gallium nitride (GaN) high electron mobility transistors (HEMTs) are quintessential prospect for the design of state-of-the-art power amplifiers (PAs). Within this context, this paper systematically investigates and realizes an integration of genetic algorithm aided artificial neural network based small-signal model into a computer-aided design (CAD) tool to elucidate the small-signal behaviour of a GaN HEMT employed class-F PA. Thereafter, an examination of amplifiers' stability and gain are expressed for the entire frequency of operation.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126127145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sharp Turn-on Diode by Steep SS “PN-Body Tied SOI FET” for Ultra-low Power RF Energy Harvesting 用于超低功率射频能量收集的陡坡SS“pn体捆结SOI场效应管”锐导二极管
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103123
Masayuki Ono, J. Ida, Takayuki Mori, K. Ishibashi
{"title":"Sharp Turn-on Diode by Steep SS “PN-Body Tied SOI FET” for Ultra-low Power RF Energy Harvesting","authors":"Masayuki Ono, J. Ida, Takayuki Mori, K. Ishibashi","doi":"10.1109/EDTM55494.2023.10103123","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103123","url":null,"abstract":"The sharp turn-on diode by our newly proposed steep subthreshold slope (SS) “PN-Body Tied (PNBT) SOI-FET” was successfully modeled for circuit simulations. We simulated the rectenna with a combination of the PNBT-diode and the high impedance (Hi-Z) antenna. The rectification efficiency over 50 % at the input of -30 dBm will be obtained. It is very high efficiency compared with the optimized conventional diodes. We fabricated the Cockcroft-Walton rectifier with PNBT-diodes. It was also confirmed that the efficiency is improved, as expected by simulations.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126719402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization and Modeling of I-V, C-V and Trapping behavior of SiC Power MOSFETs SiC功率mosfet的I-V、C-V及俘获特性的表征与建模
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10102944
Mohammmad Sajid Nazir, A. Pampori, Yawar Hayat Zarkob, Anirban Kar, Y. Chauhan
{"title":"Characterization and Modeling of I-V, C-V and Trapping behavior of SiC Power MOSFETs","authors":"Mohammmad Sajid Nazir, A. Pampori, Yawar Hayat Zarkob, Anirban Kar, Y. Chauhan","doi":"10.1109/EDTM55494.2023.10102944","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10102944","url":null,"abstract":"This paper presents a physics-based model to capture the current-voltage (I-V) and capacitance-voltage (C-V) of multiple commercially available Silicon Carbide (SiC) MOSFETs. A charge-based core model has been developed to capture the I-V characteristics of the devices. The parasitic charges and capacitances are modeled empirically to capture the C-V characteristics and kink in the gatedrain capacitance $(C_{GD})$. To study the trapping behavior, dual-pulse trap characterization is performed for multiple gate and drain quiescent conditions. A positive shift in threshold voltage $(V_{TH})$ with VGSQ is observed. Further, an RC network approach is implemented to model stress-induced changes in the I-V characteristics of the device.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126737486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cross-Temperature Reliabilities in TLC 3D NAND Flash Memory: Characterization and Solution TLC 3D NAND闪存的跨温度可靠性:表征和解决方案
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Pub Date : 2023-03-07 DOI: 10.1109/EDTM55494.2023.10103107
Yifan Guo, Kenie Xie, Xiaotong Fang, Xuepeng Zhan, Jixuan Wu, Jiezhi Chen
{"title":"Cross-Temperature Reliabilities in TLC 3D NAND Flash Memory: Characterization and Solution","authors":"Yifan Guo, Kenie Xie, Xiaotong Fang, Xuepeng Zhan, Jixuan Wu, Jiezhi Chen","doi":"10.1109/EDTM55494.2023.10103107","DOIUrl":"https://doi.org/10.1109/EDTM55494.2023.10103107","url":null,"abstract":"Temperature impacts on the reliabilities of TLC 3D NAND flash memory are investigated through cross-temperature measurements, and a simple method is proposed to estimate the optimal read voltage $(mathrm{V}_{text{opt}})$ to lower the error bits. With real chip characterizations, it is shown that $mathrm{V}_{text{opt}}$ is strongly correlated to the temperature difference between data reading and data programming, rather than the temperature itself. This indicates that $mathrm{V}_{text{opt}}$ can be obtained by using $mathrm{V}_{text{th}}$ offset between operation temperatures. The effects of the proposed scheme are also evaluated in real chips, showing that ~60% error bits can be well suppressed.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124239055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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