Characterization and Modeling of I-V, C-V and Trapping behavior of SiC Power MOSFETs

This paper presents a physics-based model to capture the current-voltage (I-V) and capacitance-voltage (C-V) of multiple commercially available Silicon Carbide (SiC) MOSFETs. A charge-based core model has been developed to capture the I-V characteristics of the devices. The parasitic charges and capacitances are modeled empirically to capture the C-V characteristics and kink in the gatedrain capacitance $(C_{GD})$. To study the trapping behavior, dual-pulse trap characterization is performed for multiple gate and drain quiescent conditions. A positive shift in threshold voltage $(V_{TH})$ with VGSQ is observed. Further, an RC network approach is implemented to model stress-induced changes in the I-V characteristics of the device.