Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications

Abstract

This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (~105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.