Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application

Abstract

Over the years, there has been much research on ferroelectric field-effect transistors (FeFETs) for memory applications. In this work, we propose a novel recessed channel FeFET with gate metal-ferroelectric $(\text{FE})-\text{metal}-\text{FE}-\text{metal}-\text{SiO}_{2}$ interlayer (IL)-silicon (MFMFMIS) gate stack, which is named a dual ferroelectric recessed channel FeFET (DF-RFeFET) aimed to increase the memory window (MW) for high-performance memory applications. With calibrated FE parameters and device models in technology computer-aided design (TCAD) simulation, we found that the DF-RFeFET can have a large MW of 3.2 V. In addition, guidelines for the DF-RFeFET design are provided in terms of the thickness ratio of the inner and outer FE layers to maximize the MW.