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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN 用于下一代WLAN的11位330MHz 8X OSR /spl Sigma/-spl Delta/调制器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705362
J. Paramesh, R. Bishop, K. Soumyanath, David Allstot
{"title":"An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN","authors":"J. Paramesh, R. Bishop, K. Soumyanath, David Allstot","doi":"10.1109/VLSIC.2006.1705362","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705362","url":null,"abstract":"A 2-2 cascaded Sigma-Delta modulator with 4-bit internal quantizers digitizes WLAN signals with 40MSPS conversion rate. Implemented in 90nm CMOS using nominal-Vt devices and metal comb capacitors, it occupies 1.3mm2 core area, achieves 67dB SNR, 63dB peak SNDR and 67dB peak SFDR at 330MHz, and dissipates 78mW from a 1.4V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124033482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses 一种稳定的SRAM单元设计，可同时抵抗读写干扰
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705287
T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, H. Akamatsu
{"title":"A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses","authors":"T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, H. Akamatsu","doi":"10.1109/VLSIC.2006.1705287","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705287","url":null,"abstract":"A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in the same column is required to a 2-port SRAM. We verified that it is difficult to provide these margins without any decrease in cell-current and any increase in cell-area penalty only by using the previously proposed techniques so far. To solve this, we have developed the new cell design technology for an 8-Tr 2-port cell in a 65-nm CMOS technology and have demonstrated that the R/W margins can be improved by 45%/70%, respectively at 0.9V, and the cell-size can be reduced by 20% compared with the conventional column-based Vdd control. Another 7-Tr cell which can reduce cell-area by 31% has been also demonstrated","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117170121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A Tunable Passive Filter for Low-Power High-Speed Equalizers 用于低功率高速均衡器的可调谐无源滤波器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705378
Ruifeng Sun, Jaejin Park, F. O’Mahony, C. Yue
{"title":"A Tunable Passive Filter for Low-Power High-Speed Equalizers","authors":"Ruifeng Sun, Jaejin Park, F. O’Mahony, C. Yue","doi":"10.1109/VLSIC.2006.1705378","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705378","url":null,"abstract":"This paper presents the design and implementation of an integrated tunable passive filter for low-power continuous-time adaptive equalization. Based on a broadband matched high-pass filter topology, a PMOS biased in linear region is used to adjust the low-frequency attenuation for equalizing channel losses. A 0.13-mum prototype demonstrates gain compensation up to 17 dB at 5 GHz without any power consumption","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123001822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Through Silicon Via and 3-D Wafer/Chip Stacking Technology 通过硅孔和三维晶圆/芯片堆叠技术
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705326
Kenji Takahashi, Masahiro Sekiguchi
{"title":"Through Silicon Via and 3-D Wafer/Chip Stacking Technology","authors":"Kenji Takahashi, Masahiro Sekiguchi","doi":"10.1109/VLSIC.2006.1705326","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705326","url":null,"abstract":"Through silicon via and 3D wafer/chip stacking technology is thought to be the essential technology of the next generation high-end semiconductors such as high-speed microprocessors and high-speed memories. However, there are many issues regarding LSI design, process integration, thermal management, and cost are under development. Cost is one of the most critical issues to apply this technology to products. We propose to categorize the through via application into three areas, i.e. low-end, middle range and high-end. High-end area that covers fast MPUs and fast memories need very small through vias to realize high-speed signal transmission between devices. Low-end area that covers image sensors, stacked memories and discrete does not always need high-speed signal transmission, but they need ultimate low cost. Thus, we developed novel through via fabrication technology employing printed circuit board (PCB) fabrication processes. The technology was applied to a CMOS image sensor wafer and successfully demonstrated","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124924751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 94
A 76 x 77mm/sup 2/, 16.85 Million Pixel CMOS APS Image Sensor 一个76 x 77mm/sup /， 1685万像素CMOS APS图像传感器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705291
S. Ay, E. Fossum
{"title":"A 76 x 77mm/sup 2/, 16.85 Million Pixel CMOS APS Image Sensor","authors":"S. Ay, E. Fossum","doi":"10.1109/VLSIC.2006.1705291","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705291","url":null,"abstract":"A 16.85 million pixel (4,096 times 4,114), single die (76mm times 77mm) CMOS active pixel sensor (APS) image sensor with 1.35Me- pixel well-depth was designed, fabricated, and tested in a 0.5mum CMOS process with a stitching option. A hybrid photodiode-photogate (HPDPG) APS pixel technology was developed. Pixel pitch was 18mum. The developed image sensor was the world's largest single-die CMOS image sensor fabricated on a 6-inch silicon wafer","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114817201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications 功率/性能/通道长度的权衡1.6至9.6Gbps的I/O链路在90nm CMOS服务器，桌面和移动应用程序
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705321
E. Yeung, K. Canagasaby, A. Tripathi, S. Chaudhuri, P. Meier, J. Prijić, V. Joshi, M. Mazumder, S. Dabral
{"title":"Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications","authors":"E. Yeung, K. Canagasaby, A. Tripathi, S. Chaudhuri, P. Meier, J. Prijić, V. Joshi, M. Mazumder, S. Dabral","doi":"10.1109/VLSIC.2006.1705321","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705321","url":null,"abstract":"Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/O links in a 1.2V 90nm CMOS test chip implementing equalized voltage-mode and current-mode drivers, TX and RX equalizers, self-biased ring oscillator and LC PLLs, and different RX clocking schemes are compared. The novel combination of voltage-mode driver (equalized or unequalized) and RX equalizer delivers the lowest power (12.1mW/Gbps at 7.2Gbps), offering a low-power option for short-distance links","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114934168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit 1.047GHz, 1.2V, 90nm CMOS，采用饱和预估电路的2路VLIW DSP核心
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705355
H. Suzuki, H. Takata, H. Shinohara, E. Teraoka, M. Matsuo, T. Yoshida, H. Sato, N. Honda, N. Masui, T. Shimizu
{"title":"1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit","authors":"H. Suzuki, H. Takata, H. Shinohara, E. Teraoka, M. Matsuo, T. Yoshida, H. Sato, N. Honda, N. Masui, T. Shimizu","doi":"10.1109/VLSIC.2006.1705355","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705355","url":null,"abstract":"1.047GHz synthesizable 2-way VLIW general purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0. 10muW/MHz at 0.8V low power operation mode","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132564280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-Band (1-6GHz), Sampled, Sliding-IF Receiver with Discrete-Time Filtering in 90nm Digital CMOS Process 多频带(1-6GHz)采样滑动中频接收机，采用90nm数字CMOS工艺进行离散时间滤波
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705394
H. Lakdawala, J.-H.C. Zhan, A. Ravi, S. Anderson, Brent R. Carlton, R.B. Nicholls, N. Yaghini, R. Bishop, Stewart S. Taylor, K. Soumyanath
{"title":"Multi-Band (1-6GHz), Sampled, Sliding-IF Receiver with Discrete-Time Filtering in 90nm Digital CMOS Process","authors":"H. Lakdawala, J.-H.C. Zhan, A. Ravi, S. Anderson, Brent R. Carlton, R.B. Nicholls, N. Yaghini, R. Bishop, Stewart S. Taylor, K. Soumyanath","doi":"10.1109/VLSIC.2006.1705394","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705394","url":null,"abstract":"A prototype 1-6GHz multi-band sampled sliding-IF receiver with discrete-time channel select filtering in a 90nm low resistivity substrate, strained-Si digital CMOS process is presented. The core receiver has an inductor-less wideband LNA front-end, a sampled mixer, and a combination of programmable poly-phase FIR and IIR filter for baseband filtering. The receiver achieves a noise figure (NF) of <13.5dB and IIP3 of >-19dBm for bands between 1-6GHz. The receiver when used in a system with an external tuned LNA (2.5dB NF) on the front end module achieves NF of <7dB, and IIP3 of >-34dBm for the WiFi bands. The die area for the entire receiver is 0.8mm2 and consumes 89mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131237934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC 一个12位32 /spl mu/W比例无关算法ADC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705305
J. Jarvinen, M. Saukoski, K. Halonen
{"title":"A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC","authors":"J. Jarvinen, M. Saukoski, K. Halonen","doi":"10.1109/VLSIC.2006.1705305","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705305","url":null,"abstract":"This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134354523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Millimeter-Wave Schottky Diode Detector in 130-nm CMOS Technology 基于130纳米CMOS技术的毫米波肖特基二极管探测器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705350
E. Seok, C. Cao, S. Sankaran, K. O
{"title":"A Millimeter-Wave Schottky Diode Detector in 130-nm CMOS Technology","authors":"E. Seok, C. Cao, S. Sankaran, K. O","doi":"10.1109/VLSIC.2006.1705350","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705350","url":null,"abstract":"A 182-GHz Schottky barrier diode detector has been demonstrated in 130-nm foundry CMOS using signals generated on-chip by modulating the bias current of a push-push voltage controlled oscillator as input. This work demonstrated that it is possible to build a detector operating near the top end of millimeter-wave range using digital CMOS","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134281840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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