Through Silicon Via and 3-D Wafer/Chip Stacking Technology

Abstract

Through silicon via and 3D wafer/chip stacking technology is thought to be the essential technology of the next generation high-end semiconductors such as high-speed microprocessors and high-speed memories. However, there are many issues regarding LSI design, process integration, thermal management, and cost are under development. Cost is one of the most critical issues to apply this technology to products. We propose to categorize the through via application into three areas, i.e. low-end, middle range and high-end. High-end area that covers fast MPUs and fast memories need very small through vias to realize high-speed signal transmission between devices. Low-end area that covers image sensors, stacked memories and discrete does not always need high-speed signal transmission, but they need ultimate low cost. Thus, we developed novel through via fabrication technology employing printed circuit board (PCB) fabrication processes. The technology was applied to a CMOS image sensor wafer and successfully demonstrated