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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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A 60GHz CMOS Differential Receiver Front-End Using On-Chip Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity 一种采用片上变压器的60GHz CMOS差分接收器前端，用于1.2伏工作，具有增强的增益和线性度
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-12-01 DOI: 10.1109/VLSIC.2006.1705351
Daquan Huang, R. Wong, Q. Gu, N. Wang, T.W. Ku, C. Chien, M. Chang
{"title":"A 60GHz CMOS Differential Receiver Front-End Using On-Chip Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity","authors":"Daquan Huang, R. Wong, Q. Gu, N. Wang, T.W. Ku, C. Chien, M. Chang","doi":"10.1109/VLSIC.2006.1705351","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705351","url":null,"abstract":"A compact 60GHz CMOS differential direct conversion receiver front-end based on eight-metal-layer interleaved on-chip transformers is realized for low voltage (1.2V) and high gain (24dB) operation with input 1dB compression point of -11dBm, noise figure of 10.5 dB and power consumption of 4.3mW/arm. Compared with prior arts in CMOS, this receiver achieves the highest gain without an output buffer, highest linearity, lowest noise, and lowest power consumption with smallest die area of 0.022mm2","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A 1mW Dual-Chopper Amplifier for a 50-/spl mu/g/spl radic/Hz Monolithic CMOS-MEMS Capacitive Accelerometer 用于50-/spl μ /g/spl径向/Hz单片CMOS-MEMS电容式加速度计的1mW双斩波放大器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705311
D. Fang, H. Qu, Huikai Xie
{"title":"A 1mW Dual-Chopper Amplifier for a 50-/spl mu/g/spl radic/Hz Monolithic CMOS-MEMS Capacitive Accelerometer","authors":"D. Fang, H. Qu, Huikai Xie","doi":"10.1109/VLSIC.2006.1705311","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705311","url":null,"abstract":"This paper reports a novel dual-chopper amplifier (DCA) for CMOS-MEMS capacitive accelerometers. A DCA prototype integrated with a single-axis accelerometer has been fabricated using TSMC 0.35 mum CMOS process. The DCA achieves a 16nV/radicHz input-referred noise at 20 Hz with a power dissipation of only 1 mW. The measured accelerometer noise floor is 50 mug/radicHz down to 5 Hz","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115659490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range 具有25%锁定范围的20 ghz注入锁定LC分频器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705364
T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, T. Kuroda
{"title":"A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range","authors":"T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, T. Kuroda","doi":"10.1109/VLSIC.2006.1705364","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705364","url":null,"abstract":"A 20-GHz injection-locked LC divider is described. A Miller divider topology was employed along with a coupling circuit to maximize the locking range. A test chip designed in a 90nm CMOS technology operates at 20 GHz with 25% locking range while consuming 6.4 mW of power","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116090225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 0.79mm/sup ~/ 29mW Real-Time Face Detection Core 一个0.79mm/sup ~/ 29mW实时人脸检测核心
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705354
Y. Hori, M. Kusaka, T. Kuroda
{"title":"A 0.79mm/sup ~/ 29mW Real-Time Face Detection Core","authors":"Y. Hori, M. Kusaka, T. Kuroda","doi":"10.1109/VLSIC.2006.1705354","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705354","url":null,"abstract":"A 0.79mm2 29mW real-time face detection core is fabricated in a 0.13mum CMOS technology. It consists of 75k gate logic, 58kbit SRAM, and the ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. The core can detect 8 faces per frame at 30 fps. Face detection accuracy is 92%","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122464036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits 分布式有源去耦电容用于数字VLSI电路的片上电源噪声消除
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705387
Jie Gu, R. Harjani, C. Kim
{"title":"Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits","authors":"Jie Gu, R. Harjani, C. Kim","doi":"10.1109/VLSIC.2006.1705387","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705387","url":null,"abstract":"A distributed active decoupling capacitor (decap) circuit is proposed to suppress the on-chip power supply noise in digital VLSI circuits. Effectiveness on suppressing local supply noise is verified from a 0.18mum test chip using multiple on-chip supply noise generators and supply noise sensors. Measurements show 4-11times boost in decap value over conventional passive decaps for frequencies up to 1 Hz. Decap area reduction of 40% is achieved","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122830103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 12b, 75MS/s Pipelined ADC Using Incomplete Settling 一个12b, 75MS/s的流水线ADC使用不完全沉降
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705390
E. Iroaga, B. Murmann
{"title":"A 12b, 75MS/s Pipelined ADC Using Incomplete Settling","authors":"E. Iroaga, B. Murmann","doi":"10.1109/VLSIC.2006.1705390","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705390","url":null,"abstract":"This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (fin = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128788054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC 一个0.9V 92dB双采样开关rc SD音频ADC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705359
Min Gyu Kim, G. Ahn, P. Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, G. Temes, U. Moon
{"title":"A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC","authors":"Min Gyu Kim, G. Ahn, P. Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, G. Temes, U. Moon","doi":"10.1109/VLSIC.2006.1705359","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705359","url":null,"abstract":"A 0.9V third-order 1.5bit delta-sigma ADC with simple dynamic element matching (DEM) is presented. A fully-differential low-voltage double-sampling structure avoids use of clock boosting or bootstrapping. It operates from 0.65V to 1.5V supply with minimal performance degradation. The prototype IC implemented in a 0.13mum CMOS process achieves 92dB DR, 91dB SNR and 89dB SNDR, while consuming 1.5mW from a 0.9V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124619836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/ 70GOPS, 34mW多载波MIMO芯片，3.5mm/sup ~/
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705358
D. Markovic, R. Brodersen, B. Nikolić
{"title":"A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/","authors":"D. Markovic, R. Brodersen, B. Nikolić","doi":"10.1109/VLSIC.2006.1705358","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705358","url":null,"abstract":"An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN is described. The chip implements a 4times4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented with 0.5M gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250Mbps over 16MHz band","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124745817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 0.5 V 900 MHz CMOS Receiver Front End 一个0.5 V 900 MHz CMOS接收器前端
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705393
N. Stanic, P. Kinget, Y. Tsividis
{"title":"A 0.5 V 900 MHz CMOS Receiver Front End","authors":"N. Stanic, P. Kinget, Y. Tsividis","doi":"10.1109/VLSIC.2006.1705393","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705393","url":null,"abstract":"A 900 MHz RF receiver front end including an LNA, downconversion mixer and associated LO buffers is presented. All circuits operate from a 0.5 V supply without any internal voltage boosting. The circuit is designed in 0.18 mum standard CMOS. It achieves a conversion gain of 12 dB, an IIP3 of -14 dBm and a noise figure of 9 dB. The circuit, including the LO buffers, dissipates 7.4 mW and occupies an active area of 0.43 mm2","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125646226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
PLL On-Chip Jitter Measurement: Analysis and Design 锁相环片上抖动测量:分析与设计
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705318
S. Vamvakos, V. Stojanović, J. Zerbe, C. Werner, D. Draper, B. Nikolić
{"title":"PLL On-Chip Jitter Measurement: Analysis and Design","authors":"S. Vamvakos, V. Stojanović, J. Zerbe, C. Werner, D. Draper, B. Nikolić","doi":"10.1109/VLSIC.2006.1705318","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705318","url":null,"abstract":"Analysis of on-chip jitter measurements based on the dead-zone method reveals potentially large errors in the jitter variance estimate, when the jitter distribution is changing or not known a priori. To overcome this, a more accurate variance estimation method is proposed and experimentally verified. The residual error, caused by the correlated noise between the PLL and the measurement circuit, is fully characterized and circuit topologies are proposed to mitigate this type of error","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"249 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133912170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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