一个12b, 75MS/s的流水线ADC使用不完全沉降

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705390

E. Iroaga, B. Murmann

{"title":"一个12b, 75MS/s的流水线ADC使用不完全沉降","authors":"E. Iroaga, B. Murmann","doi":"10.1109/VLSIC.2006.1705390","DOIUrl":null,"url":null,"abstract":"This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (fin = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A 12b, 75MS/s Pipelined ADC Using Incomplete Settling\",\"authors\":\"E. Iroaga, B. Murmann\",\"doi\":\"10.1109/VLSIC.2006.1705390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (fin = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 17

摘要

本文提出了一种利用不完全沉降实现超低功率剩余放大的混合信号技术。在本文提出的12位75 ms /s原型ADC的第一级中，所采用的开环增益级在3V电源下仅耗散2.9mW，比典型运算放大器实现的功耗降低94%。完整的流水线ADC的测量信噪比为66dB (fin = 1MHz)，功耗为273mW，在0.35 mm CMOS中占地7.9mm

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A 12b, 75MS/s Pipelined ADC Using Incomplete Settling

This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (fin = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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