A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705358

D. Markovic, R. Brodersen, B. Nikolić

引用次数: 16

Abstract

An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN is described. The chip implements a 4times4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented with 0.5M gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250Mbps over 16MHz band

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70GOPS, 34mW多载波MIMO芯片，3.5mm/sup ~/

描述了一种多天线无线局域网MIMO基带处理的ASIC实现。该芯片采用4倍自适应奇异值分解(SVD)算法，结合功率和面积最小化，在3.5mm2的90nm CMOS中实现2.1GOPS/mW的功率效率。在100MHz时钟和385mV电源下，使用0.5M栅极实现70GOPS的计算吞吐量，功耗为34mW。在最佳信道条件下，实现的算法可以在16MHz频段上提供高达250Mbps的传输

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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