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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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Supply Voltage Adjustment Technique for Low Power Consumption and Its Application to SOCs with Multiple Threshold Voltage CMOS 低功耗电源电压调整技术及其在多阈值CMOS soc中的应用
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705383
H. Okano, T. Shiota, Y. Kawabe, W. Shibamoto, T. Hashimoto, A. Inoue
{"title":"Supply Voltage Adjustment Technique for Low Power Consumption and Its Application to SOCs with Multiple Threshold Voltage CMOS","authors":"H. Okano, T. Shiota, Y. Kawabe, W. Shibamoto, T. Hashimoto, A. Inoue","doi":"10.1109/VLSIC.2006.1705383","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705383","url":null,"abstract":"An energy-saving system for SOCs using multiple threshold voltage CMOS was developed. It equips process sensors and process-voltage conversion table generated from static timing analysis results, and adjusts. The supply voltage according to die-to-die process variation. We applied this system to an embedded dual-core microprocessor using 90nm triple Threshold voltage CMOS technology. When the microprocessor executes video stream decoding program, 17% power reduction was measured with dies of typical process condition","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130643431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC 65 nm超高密度双端口SRAM, 0.71um/sup ~/ 8T-Cell用于SoC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705344
K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara
{"title":"A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC","authors":"K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara","doi":"10.1109/VLSIC.2006.1705344","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705344","url":null,"abstract":"We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71mum2 8T-DP-cell, which cell size is 1.44times larger than 6T-single-port (SP) cell","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133985278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Notice of Violation of IEEE Publication Principles9.75/10.6GHz SiGe PLL for LNB Satellite Front-Ends Using Half-Rate Oscillators 使用半速率振荡器的LNB卫星前端9.75/10.6 ghz SiGe锁相环违反IEEE发布原则的通知
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705302
A. Maxim, M. Gheorghe, C. Turinici
{"title":"Notice of Violation of IEEE Publication Principles9.75/10.6GHz SiGe PLL for LNB Satellite Front-Ends Using Half-Rate Oscillators","authors":"A. Maxim, M. Gheorghe, C. Turinici","doi":"10.1109/VLSIC.2006.1705302","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705302","url":null,"abstract":"A fully-integrated frequency synthesizer for DBS satellite front-ends was realized in a low cost 50GHz fT SiGe process. Two half-rate VCOs followed by Gilbert frequency doublers generate the 9.75/10.6 GHz LO signals with lower phase noise than a full-rate oscillator. The loop filter was integrated on-chip by using a passive feed-forward architecture, which provides a noiseless resistor multiplication","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134266614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Injection-Locked Frequency Dividers based on Ring Oscillators with Optimum Injection for Wide Lock Range 基于环振荡器的宽锁相范围最佳注入锁相分频器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705366
Ahmad Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, A. A. Abidi
{"title":"Injection-Locked Frequency Dividers based on Ring Oscillators with Optimum Injection for Wide Lock Range","authors":"Ahmad Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, A. A. Abidi","doi":"10.1109/VLSIC.2006.1705366","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705366","url":null,"abstract":"Divide-by-2 and divide-by-6 ring oscillators use multi-phase injection to operate from near DC to 1.7 and 1.2 GHz input frequencies, respectively. In 0.13-mum CMOS, the circuits consume 0.25 mA per stage","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132865638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 10MS/s 11-b 0.19mm/sup 2/ Algorithmic ADC with Improved Clocking 一个10MS/s 11-b 0.19mm/sup /算法ADC与改进的时钟
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705306
Min Gyu Kim, P. Hanumolu, U. Moon
{"title":"A 10MS/s 11-b 0.19mm/sup 2/ Algorithmic ADC with Improved Clocking","authors":"Min Gyu Kim, P. Hanumolu, U. Moon","doi":"10.1109/VLSIC.2006.1705306","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705306","url":null,"abstract":"A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13mum thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133534590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-/spl mu/m CMOS 0.18-/spl mu/m CMOS的9.5 db 50 ghz矩阵分布式放大器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705352
Jun-Chau Chien, Tai-Yuan Chen, Liang-Hung Lu
{"title":"A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-/spl mu/m CMOS","authors":"Jun-Chau Chien, Tai-Yuan Chen, Liang-Hung Lu","doi":"10.1109/VLSIC.2006.1705352","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705352","url":null,"abstract":"Implemented in a 0.18-mum CMOS process, a 2times4 matrix amplifier is presented in this paper. Due to the use of the second-tier gain cells in the distributed amplifier architecture, the proposed circuit exhibits a remarkable nominal gain of 9.5 dB with a 3-dB bandwidth of 50 GHz while maintaining input and output return losses better than 10 dB over the entire frequency band. A gain-bandwidth product of 150 GHz is demonstrated in this work","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits 一种65nm SoC嵌入式6T-SRAM设计，用于制造读写单元稳定电路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705290
S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara
{"title":"A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits","authors":"S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara","doi":"10.1109/VLSIC.2006.1705290","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705290","url":null,"abstract":"We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 mum2 SRAM cell with a beta ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115885639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
A Low Power 4.2Gb/s/pin Parallel Link Using Three-Level Differential Encoding 采用三电平差分编码的低功耗4.2Gb/s/引脚并行链路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705320
Sotirios Zogopoulos, W. Namgoong
{"title":"A Low Power 4.2Gb/s/pin Parallel Link Using Three-Level Differential Encoding","authors":"Sotirios Zogopoulos, W. Namgoong","doi":"10.1109/VLSIC.2006.1705320","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705320","url":null,"abstract":"A three-level encoding scheme is proposed to reduce power and increase the data rate in high-speed parallel transceiver system. The proposed encoding scheme transmits 3-bit of information via four pins to overcome the two major problems in single-ended links - reference ambiguity and power line fluctuations - while minimizing power consumption and the effects of inter-symbol interference (ISI). The proposed parallel link, which is designed in 0.18mum CMOS process, achieves a data rate of 4.2Gb/s/pin while dissipating 17.1mW/Gb/s","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121823398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A High Dynamic Range CMOS Image Sensor with In-Pixel Floating-Node Analog Memory for Pixel Level Integration Time Control 基于像素级浮动节点模拟存储器的高动态范围CMOS图像传感器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705294
Sang-Wook Han, Seong-Jin Kim, Jaehyuk Choi, C. Kim, E. Yoon
{"title":"A High Dynamic Range CMOS Image Sensor with In-Pixel Floating-Node Analog Memory for Pixel Level Integration Time Control","authors":"Sang-Wook Han, Seong-Jin Kim, Jaehyuk Choi, C. Kim, E. Yoon","doi":"10.1109/VLSIC.2006.1705294","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705294","url":null,"abstract":"In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. We can implement true CDS technique to reduce reset noise without any additional hardware because we use a floating-node parasitic capacitor as an analog memory. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB. To the best of our knowledge, this is the first report on the use of pixel-node parasitic capacitor as an analog memory for the extension of dynamic range","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131792151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Watchdog Sensor for Assuring the Quality of Various Perishables with Subthreshold CMOS Circuits 用亚阈值CMOS电路保证各种易腐品质量的看门狗传感器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705357
K. Ueno, T. Hirose, T. Asai, Y. Amemiya
{"title":"A Watchdog Sensor for Assuring the Quality of Various Perishables with Subthreshold CMOS Circuits","authors":"K. Ueno, T. Hirose, T. Asai, Y. Amemiya","doi":"10.1109/VLSIC.2006.1705357","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705357","url":null,"abstract":"We developed a CMOS integrated-circuit sensor that emulates the change in quality of various perishables. This sensor is attached to perishable goods such as farm and marine products and is carried from producers to consumers along with the goods. During their distribution process, the sensor experiences the surrounding temperature and emulates the deterioration of the goods caused by the surrounding temperatures. By reading the output of the sensor, consumers can determine whether the goods are fresh or not. This sensor consists of subthreshold CMOS circuits with a low-power consumption of 5muW or less","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132435975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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