{"title":"A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-/spl mu/m CMOS","authors":"Jun-Chau Chien, Tai-Yuan Chen, Liang-Hung Lu","doi":"10.1109/VLSIC.2006.1705352","DOIUrl":null,"url":null,"abstract":"Implemented in a 0.18-mum CMOS process, a 2times4 matrix amplifier is presented in this paper. Due to the use of the second-tier gain cells in the distributed amplifier architecture, the proposed circuit exhibits a remarkable nominal gain of 9.5 dB with a 3-dB bandwidth of 50 GHz while maintaining input and output return losses better than 10 dB over the entire frequency band. A gain-bandwidth product of 150 GHz is demonstrated in this work","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"165 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705352","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
Implemented in a 0.18-mum CMOS process, a 2times4 matrix amplifier is presented in this paper. Due to the use of the second-tier gain cells in the distributed amplifier architecture, the proposed circuit exhibits a remarkable nominal gain of 9.5 dB with a 3-dB bandwidth of 50 GHz while maintaining input and output return losses better than 10 dB over the entire frequency band. A gain-bandwidth product of 150 GHz is demonstrated in this work