A Low Power 4.2Gb/s/pin Parallel Link Using Three-Level Differential Encoding

Abstract

A three-level encoding scheme is proposed to reduce power and increase the data rate in high-speed parallel transceiver system. The proposed encoding scheme transmits 3-bit of information via four pins to overcome the two major problems in single-ended links - reference ambiguity and power line fluctuations - while minimizing power consumption and the effects of inter-symbol interference (ISI). The proposed parallel link, which is designed in 0.18mum CMOS process, achieves a data rate of 4.2Gb/s/pin while dissipating 17.1mW/Gb/s