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引用次数: 5
摘要
为了在高速并行收发系统中降低功耗，提高数据速率，提出了一种三级编码方案。提出的编码方案通过4个引脚传输3位信息，以克服单端链路中的两个主要问题——参考模糊和电力线波动，同时最大限度地降低功耗和码间干扰(ISI)的影响。该并行链路采用0.18 μ m CMOS工艺设计，数据速率为4.2Gb/s/引脚，功耗为17.1mW/Gb/s
A Low Power 4.2Gb/s/pin Parallel Link Using Three-Level Differential Encoding
A three-level encoding scheme is proposed to reduce power and increase the data rate in high-speed parallel transceiver system. The proposed encoding scheme transmits 3-bit of information via four pins to overcome the two major problems in single-ended links - reference ambiguity and power line fluctuations - while minimizing power consumption and the effects of inter-symbol interference (ISI). The proposed parallel link, which is designed in 0.18mum CMOS process, achieves a data rate of 4.2Gb/s/pin while dissipating 17.1mW/Gb/s
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