一个0.9V 92dB双采样开关rc SD音频ADC

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705359

Min Gyu Kim, G. Ahn, P. Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, G. Temes, U. Moon

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引用次数: 12

摘要

提出了一种基于简单动态单元匹配(DEM)的0.9V三阶1.5位δ - σ ADC。全差分低压双采样结构避免了时钟升压或自举的使用。它的工作电压从0.65V到1.5V，性能下降最小。在0.13 μ m CMOS工艺中实现的原型IC实现了92dB DR, 91dB SNR和89dB SNDR，同时从0.9V电源消耗1.5mW

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A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC

A 0.9V third-order 1.5bit delta-sigma ADC with simple dynamic element matching (DEM) is presented. A fully-differential low-voltage double-sampling structure avoids use of clock boosting or bootstrapping. It operates from 0.65V to 1.5V supply with minimal performance degradation. The prototype IC implemented in a 0.13mum CMOS process achieves 92dB DR, 91dB SNR and 89dB SNDR, while consuming 1.5mW from a 0.9V supply

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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