{"title":"一个0.5 V 900 MHz CMOS接收器前端","authors":"N. Stanic, P. Kinget, Y. Tsividis","doi":"10.1109/VLSIC.2006.1705393","DOIUrl":null,"url":null,"abstract":"A 900 MHz RF receiver front end including an LNA, downconversion mixer and associated LO buffers is presented. All circuits operate from a 0.5 V supply without any internal voltage boosting. The circuit is designed in 0.18 mum standard CMOS. It achieves a conversion gain of 12 dB, an IIP3 of -14 dBm and a noise figure of 9 dB. The circuit, including the LO buffers, dissipates 7.4 mW and occupies an active area of 0.43 mm2","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"A 0.5 V 900 MHz CMOS Receiver Front End\",\"authors\":\"N. Stanic, P. Kinget, Y. Tsividis\",\"doi\":\"10.1109/VLSIC.2006.1705393\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 900 MHz RF receiver front end including an LNA, downconversion mixer and associated LO buffers is presented. All circuits operate from a 0.5 V supply without any internal voltage boosting. The circuit is designed in 0.18 mum standard CMOS. It achieves a conversion gain of 12 dB, an IIP3 of -14 dBm and a noise figure of 9 dB. The circuit, including the LO buffers, dissipates 7.4 mW and occupies an active area of 0.43 mm2\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"2009 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705393\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 900 MHz RF receiver front end including an LNA, downconversion mixer and associated LO buffers is presented. All circuits operate from a 0.5 V supply without any internal voltage boosting. The circuit is designed in 0.18 mum standard CMOS. It achieves a conversion gain of 12 dB, an IIP3 of -14 dBm and a noise figure of 9 dB. The circuit, including the LO buffers, dissipates 7.4 mW and occupies an active area of 0.43 mm2