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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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A 1.2V 37-38.5GHz 8-Phase Clock Generator in 0.13/spl mu/ m CMOS Technology 基于0.13/spl mu/ m CMOS技术的1.2V 37-38.5GHz 8相时钟发生器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705295
Chihun Lee, Lan-Cho Chou, Shen-Iuan Liu, Chun-Lin Ko, Y. Juang, Chin-Fong Chiu
{"title":"A 1.2V 37-38.5GHz 8-Phase Clock Generator in 0.13/spl mu/ m CMOS Technology","authors":"Chihun Lee, Lan-Cho Chou, Shen-Iuan Liu, Chun-Lin Ko, Y. Juang, Chin-Fong Chiu","doi":"10.1109/VLSIC.2006.1705295","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705295","url":null,"abstract":"A 37-38.5GHz octave-phase clock generator is presented. An octave-phase LC voltage-controlled oscillator and the split-load divider are presented. The proposed PD improves the static phase error and enhances the gain. The clock generator has been fabricated in 0.13mum CMOS technology. It achieves the rms jitter of 0.24ps at 38GHz while consuming 51.6mW without buffers from a 1.2V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133967571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 14-Bit 5MS/s Continuous-Time Delta-Sigma A/D Modulator 一个14位5MS/s连续时间Delta-Sigma A/D调制器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705361
Zhimin Li, T. Fiez
{"title":"A 14-Bit 5MS/s Continuous-Time Delta-Sigma A/D Modulator","authors":"Zhimin Li, T. Fiez","doi":"10.1109/VLSIC.2006.1705361","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705361","url":null,"abstract":"A continuous-time delta-sigma A/D modulator providing 85dB DR with 5MS/s output rate in a 2.5V 0.25mum CMOS process is presented. The modulator has a single-stage, dual-loop architecture allowing nearly one clock period excess loop delay. A multi-bit quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome process variation. Calibration is implemented to suppress DAC mismatch. Clocked at 60MHz, the chip consumes 50 mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133267043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Duty-Cycle Correction Circuit for High-Frequency Clocks 高频时钟的占空比校正电路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705332
K. Agarwal, R. Montoye
{"title":"A Duty-Cycle Correction Circuit for High-Frequency Clocks","authors":"K. Agarwal, R. Montoye","doi":"10.1109/VLSIC.2006.1705332","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705332","url":null,"abstract":"We present a circuit to control duty-cycle of high-frequency clocks with very fine resolution. The proposed duty-cycle detection and correction circuits are digital and do not require external references and matching devices. The circuits are designed to compensate for duty-cycle uncertainties in a floating point unit implemented using limited switch dynamic logic (LSDL) (Belloumini, 2005). The results show that the circuit can correct the duty-cycle of an 8-GHz clock with plusmn0.8% accuracy for an input range of 25% to 75%","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116023264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A Register File with 8.4GHz Throughput for Efficient Instruction Scheduling in a Pentium~ 4 Processor Pentium~ 4处理器中8.4GHz吞吐量的高效指令调度寄存器文件
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705373
N. Nintunze, G. Pham
{"title":"A Register File with 8.4GHz Throughput for Efficient Instruction Scheduling in a Pentium~ 4 Processor","authors":"N. Nintunze, G. Pham","doi":"10.1109/VLSIC.2006.1705373","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705373","url":null,"abstract":"This paper describes a unique register file (RF) for ping-pong operation in 65nm CMOS process. The merged ping-pong reduces array width by 50%, doubles the frequency of access, and allows for same phase read and write. Implementation as a dependency matrix allows for all read wordlines to be asserted at once. A bypass scheme merged with the bitline contributes to a 27% leakage saving","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132069268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Coupled Inverter Ring I/Q Oscillator for Low Power Frequency Synthesis 用于低功率频率合成的耦合逆变环I/Q振荡器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705365
J. Xu, S. Verma, T. Lee
{"title":"Coupled Inverter Ring I/Q Oscillator for Low Power Frequency Synthesis","authors":"J. Xu, S. Verma, T. Lee","doi":"10.1109/VLSIC.2006.1705365","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705365","url":null,"abstract":"A novel 12-stage VCO with in-phase and quadrature outputs at the 3rd harmonic of the oscillating frequency is presented. It employs coupled inverter rings. A new linear model of coupled inverter rings is developed to identify all possible oscillating modes and their frequencies using the Barkhausen criterion. A frequency synthesizer implemented in 0.18mum CMOS with such a VCO has wide tuning range, and consumes only 2.8mA from a 1.5V supply to generate 2.4GHz differential I/Q outputs","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129241867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 300 nW, 12 ppm//spl deg/C Voltage Reference in a Digital 0.35 /spl mu/m CMOS Process 一个300 nW, 12 ppm//spl度/C的数字0.35 /spl mu/m CMOS工艺电压基准
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705322
G. de Vita, G. Iannaccone, P. Andreani
{"title":"A 300 nW, 12 ppm//spl deg/C Voltage Reference in a Digital 0.35 /spl mu/m CMOS Process","authors":"G. de Vita, G. Iannaccone, P. Andreani","doi":"10.1109/VLSIC.2006.1705322","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705322","url":null,"abstract":"A voltage reference has been implemented in a standard 0.35 mum CMOS process. A temperature coefficient of 12 ppm/degC is achieved in virtue of a complete suppression of the temperature dependence of the carrier mobility. The line sensitivity is 0.46 %/V and the maximum supply current, measured at 80degC, is 130 nA. The PSSR at 100 Hz and 10 MHz is -59 dB and -52 dB, respectively","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128762453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A 0.5-V 1-Msample/s 60-dB SNDR Track-and-Hold Circuit 一个0.5 v 1 msample /s 60 db SNDR跟踪保持电路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705304
S. Chatterjee, P. Kinget
{"title":"A 0.5-V 1-Msample/s 60-dB SNDR Track-and-Hold Circuit","authors":"S. Chatterjee, P. Kinget","doi":"10.1109/VLSIC.2006.1705304","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705304","url":null,"abstract":"A 0.5V 1Msps track-and-hold (T/H) circuit with a 60dB SNDR is presented. The fully-differential circuit is implemented in a 0.25mum CMOS technology, with standard 0.6V VT devices, and uses true low voltage design techniques i.e. with no clock and no voltage boosting","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116125461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Analog Frontend Chip for a MEMS-Based Parallel Scanning-Probe Data-Storage System 基于mems的并行扫描探针数据存储系统的模拟前端芯片
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705310
C. Hagleitner, T. Bonaccio, A. Pantazi, A. Sebastian, E. Eleftheriou
{"title":"An Analog Frontend Chip for a MEMS-Based Parallel Scanning-Probe Data-Storage System","authors":"C. Hagleitner, T. Bonaccio, A. Pantazi, A. Sebastian, E. Eleftheriou","doi":"10.1109/VLSIC.2006.1705310","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705310","url":null,"abstract":"We present a 32-channel analog frontend chip for a parallel scanning-probe data-storage system (\"millipede\"-project). The chip include all circuitry required to control the thermomechanical write-process that forms nanoscale indentations in a polymer surface. The on-chip read-channel circuitry is able to reliably detect the tiny signal-current obtained with the thermoelectrical read-process in the presence of a 1000 times larger bias current","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"124 27","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113940072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 24-GHz Transmitter with an On-Chip Antenna in 130-nm CMOS 带有片上天线的130nm CMOS的24ghz发射机
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705353
C. Cao, Yanping Ding, Xiuge Yang, Jau-Jr Lin, A. Verma, Jenshan Lin, F. Martin, K. O
{"title":"A 24-GHz Transmitter with an On-Chip Antenna in 130-nm CMOS","authors":"C. Cao, Yanping Ding, Xiuge Yang, Jau-Jr Lin, A. Verma, Jenshan Lin, F. Martin, K. O","doi":"10.1109/VLSIC.2006.1705353","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705353","url":null,"abstract":"A transmitter with an on-chip dipole antenna operating in the 24-GHz ISM band was fabricated in 130-nm CMOS. It provides 8-dBm output power and 7.7% rms EVM while consuming 100-mW power. An integer-N synthesizer consuming 36-mW power is also integrated. The signal transmitted by the chip has been picked up 95 m away using a horn antenna. This work demonstrates that communication between a base station and an integrated circuit with on-chip antenna over a distance of 100 m is possible","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133463312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A 1.2V, 10.8mW, 500kHz Sigma-Delta Modulator with 84dB SNDR and 96dB SFDR 1.2V, 10.8mW, 500kHz Sigma-Delta调制器，SNDR 84dB, SFDR 96dB
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705360
C. Tsang, Y. Chiu, B. Nikolić
{"title":"A 1.2V, 10.8mW, 500kHz Sigma-Delta Modulator with 84dB SNDR and 96dB SFDR","authors":"C. Tsang, Y. Chiu, B. Nikolić","doi":"10.1109/VLSIC.2006.1705360","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705360","url":null,"abstract":"A 1.2V switched-capacitor sigma-delta modulator achieves 96dB peak SFDR and 84dB peak SNDR at 1 MS/s in a 0.13mum 6M1P general-purpose CMOS process. The high linearity is achieved by using high-gain op-amps and bootstrapped sampling switches. The power dissipation is 10.8mW at 64MHz clock frequency, excluding the voltage references","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134039005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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