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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor 为双核多线程Xeon/sup /处理器提供65nm 16MB片上L3缓存
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705342
J. Chang, Ming Huang, J. Shoemaker, J. Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, R. Ganesan, G. Leong, V. Lukka, S. Rusu, D. Srivastava
{"title":"The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor","authors":"J. Chang, Ming Huang, J. Shoemaker, J. Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, R. Ganesan, G. Leong, V. Lukka, S. Rusu, D. Srivastava","doi":"10.1109/VLSIC.2006.1705342","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705342","url":null,"abstract":"The 16-way set associative, single-ported 16MB cache for the dual-core Xeonreg processor uses a 0.624mum2 cell in a 65nm 8-metal technology. Only 0.8% of the cache is powered up for an access. Sleep transistors are used in the SRAM array and peripherals. Dynamic Pellston with a history buffer protects the cache from latent defects and infant mortality failures","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131995426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers 用于串行链路接收机的10gb /s CMOS合并自适应均衡器/CDR电路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705376
S. Gondi, B. Razavi
{"title":"A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers","authors":"S. Gondi, B. Razavi","doi":"10.1109/VLSIC.2006.1705376","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705376","url":null,"abstract":"A merged equalizer/CDR circuit employs a parallel-path equalizer and triple-loop adaptation to achieve a binary data rate of 10 Gb/s. Realized in 0.13mum CMOS technology, the circuit adapts to FR4 trace lengths up to 24 inches with BER<10-13 while consuming 133 mW from a 1.6-V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115608639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 200Mb/s-2Gb/s Oversampling RX with Digitally Self-Adapting Equalizer in 0.18/spl mu/m CMOS Technology 基于0.18/spl μ m CMOS技术的200Mb/s- 2gb /s过采样RX数字自适应均衡器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705377
G. den Besten, F. Gerfers, J. Conder, A.J. Kollmann, P. Petkov
{"title":"A 200Mb/s-2Gb/s Oversampling RX with Digitally Self-Adapting Equalizer in 0.18/spl mu/m CMOS Technology","authors":"G. den Besten, F. Gerfers, J. Conder, A.J. Kollmann, P. Petkov","doi":"10.1109/VLSIC.2006.1705377","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705377","url":null,"abstract":"This paper presents a 6x OSR receiver for 200M-2Gb/s, comprising an adaptive equalizer that is auto-calibrating on sample data statistics. This robust and highly digitized receiver is demonstrated in 0.18mum CMOS and can equalize variable cable losses up to 22dB. The self-adaptive equalizer solution occupies only 0.08mm2 and consumes 9-16mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor 175 GMACS/mW电荷模式绝热混合信号阵列处理器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705329
Rafal Karakiewicz, R. Genov, Adeel Abbas, Gert Cauwenberghs
{"title":"175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor","authors":"Rafal Karakiewicz, R. Genov, Adeel Abbas, Gert Cauwenberghs","doi":"10.1109/VLSIC.2006.1705329","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705329","url":null,"abstract":"An adiabatic charge-recycling mixed-signal array with integrated resonant clock generator delivers 175 GMACS (multiply-and-accumulates per second) throughput for every mW of power, a ten-fold improvement over the dynamic power incurred when resonant line drivers are replaced with CMOS drivers. The 3-T CID/DRAM cell provides non-destructive 1b-1b multiply accumulation, and integrated quantizers yield 8-bit outputs with +/- 1 LSB worst-case mismatch. The 256 times 512 four-quadrant array is embedded in a processor for template-based face detection","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116976416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 14-b 150 MS/s CMOS DAC with Digital Background Calibration 带数字背景校准的14-b 150ms /s CMOS DAC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705307
Hsing-Hung Chen, Jaesik Lee, J. Weiner, Young-Kai Chen, Jiunn-Tsair Chen
{"title":"A 14-b 150 MS/s CMOS DAC with Digital Background Calibration","authors":"Hsing-Hung Chen, Jaesik Lee, J. Weiner, Young-Kai Chen, Jiunn-Tsair Chen","doi":"10.1109/VLSIC.2006.1705307","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705307","url":null,"abstract":"A 14-b 150MS/s current-steering DAC with background calibration technique is demonstrated. Digital background calibration loop trims the static performance less than plusmn 0.55 LSB. The DAC achieves the spurious free dynamic range (SFDR) of 81dB at 1.6MHz and 67dB at 48.75MHz for sampling rate of 150MS/s. The DAC is implemented in a 0.35 mum CMOS process and active area is a 2.4times1.2 mm2","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115770365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 0.88nW/pixel, 99.6 dB Linear-Dynamic-Range Fully-Digital Image Sensor Employing a Pixel-Level Sigma-Delta ADC 采用像素级Sigma-Delta ADC的0.88nW/pixel, 99.6 dB线性动态范围全数字图像传感器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705293
Z. Ignjatovic, M. Bocko
{"title":"A 0.88nW/pixel, 99.6 dB Linear-Dynamic-Range Fully-Digital Image Sensor Employing a Pixel-Level Sigma-Delta ADC","authors":"Z. Ignjatovic, M. Bocko","doi":"10.1109/VLSIC.2006.1705293","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705293","url":null,"abstract":"We describe a CMOS image sensor employing pixel-level SigmaDelta analog to digital conversion. The design has high fill factor (31%), zero DC offset fixed pattern noise and reduced reset and transistor readout noise in comparison to other analog and digital imager readout techniques. The SigmaDelta pixel design also has low power consumption: 0.88 nW/pixel at 30 fps, high dynamic range of 16 bits, intrinsic linearity, and relative insensitivity to process variations","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116097706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Fully Integrated 10Gbps Receiver with Adaptive Optical Dispersion Equalizer in 0.13/spl mu/m CMOS 基于0.13/spl mu/m CMOS的全集成10Gbps自适应色散均衡器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705338
A. Momtaz, D. Chung, N. Kocaman, M. Caresosa, J. Cao, Bo Zhang, I. Fujimori
{"title":"A Fully Integrated 10Gbps Receiver with Adaptive Optical Dispersion Equalizer in 0.13/spl mu/m CMOS","authors":"A. Momtaz, D. Chung, N. Kocaman, M. Caresosa, J. Cao, Bo Zhang, I. Fujimori","doi":"10.1109/VLSIC.2006.1705338","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705338","url":null,"abstract":"A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10-12 . Use of analog equalizer with digital adaptation garners total power dissipation of 950mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122615864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Single-Chip Gaussian Monocycle Pulse Transmitter Using 0.18 /spl m/m CMOS Technology for Intra/Interchip UWB Communication 采用0.18 /spl m/m CMOS技术实现片内/片间超宽带通信的单片高斯单周脉冲发射机
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705381
P. K. Saha, N. Sasaki, T. Kikkawa
{"title":"A Single-Chip Gaussian Monocycle Pulse Transmitter Using 0.18 /spl m/m CMOS Technology for Intra/Interchip UWB Communication","authors":"P. K. Saha, N. Sasaki, T. Kikkawa","doi":"10.1109/VLSIC.2006.1705381","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705381","url":null,"abstract":"An ultra short Gaussian monocycle pulse (GMP) of 280 ps duration, -20.2dB ringing level and 3.6 GHz center frequency was generated in 0.18 mum CMOS technology for single chip implementation of impulse radio based ultra-wideband (IR-UWB) transceiver system. The transmission and reception of the generated GMP at 1 mm distance in Si substrate by integrated dipole antennas were successfully demonstrated at a pulse repetition rate of 1.16 Gbps for the first time","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129951475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 1-ps Resolution On-Chip Sampling Oscilloscope with 64:1 Tunable Sampling Range Based on Ramp Waveform Division Scheme 基于斜坡波形分割方案的64:1可调采样范围的1-ps分辨率片上采样示波器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705312
K. Inagaki, D. Antono, M. Takamiya, S. Kumashiro, T. Sakurai
{"title":"A 1-ps Resolution On-Chip Sampling Oscilloscope with 64:1 Tunable Sampling Range Based on Ramp Waveform Division Scheme","authors":"K. Inagaki, D. Antono, M. Takamiya, S. Kumashiro, T. Sakurai","doi":"10.1109/VLSIC.2006.1705312","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705312","url":null,"abstract":"An on-chip sampling oscilloscope with lps timing resolution is realized in 90nm CMOS process based on a proposed ramp waveform division scheme for precise signal integrity and power-line integrity measurement. The resolution in time is variable from 1ps to 64ps in 64 steps. A novel on-chip inductance measurement procedure is also proposed","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link 电感耦合CMOS链路中降低功耗的菊花链
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705314
M. Inoue, N. Miura, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, T. Kuroda
{"title":"Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link","authors":"M. Inoue, N. Miura, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, T. Kuroda","doi":"10.1109/VLSIC.2006.1705314","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705314","url":null,"abstract":"This paper discusses a daisy chain of current-drive transmitters in inductive-coupling CMOS links. Current is reused by multiple transmitters. 8 transceivers are arranged with a pitch of 20mum in 0.18mum CMOS. Transmit power is saved by 35% without sacrificing data rate (1Gb/s/ch) and BER (<10-12) by having 4 transmitters daisy chained","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127081880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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