The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705342

J. Chang, Ming Huang, J. Shoemaker, J. Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, R. Ganesan, G. Leong, V. Lukka, S. Rusu, D. Srivastava

引用次数: 13

Abstract

The 16-way set associative, single-ported 16MB cache for the dual-core Xeonreg processor uses a 0.624mum2 cell in a 65nm 8-metal technology. Only 0.8% of the cache is powered up for an access. Sleep transistors are used in the SRAM array and peripherals. Dynamic Pellston with a history buffer protects the cache from latent defects and infant mortality failures

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为双核多线程Xeon/sup /处理器提供65nm 16MB片上L3缓存

双核Xeonreg处理器的16路集合关联，单端口16MB缓存使用65nm 8金属技术的0.624mum2单元。只有0.8%的缓存为访问打开了电源。休眠晶体管用于SRAM阵列和外设。具有历史缓冲的动态Pellston保护缓存免受潜在缺陷和婴儿死亡率失败的影响

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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