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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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An Integrated 1.8V to 3.3V Regulated Voltage Doubler Using Active Diodes and Dual-Loop Voltage Follower for Switch-Capacitive Load 集成1.8V至3.3V稳压倍频器，采用有源二极管和双环电压跟随器，用于开关电容负载
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705324
Yat-Hei Lam, W. Ki, C. Tsui
{"title":"An Integrated 1.8V to 3.3V Regulated Voltage Doubler Using Active Diodes and Dual-Loop Voltage Follower for Switch-Capacitive Load","authors":"Yat-Hei Lam, W. Ki, C. Tsui","doi":"10.1109/VLSIC.2006.1705324","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705324","url":null,"abstract":"An integrated 1.8V to 3.3V regulated voltage doubler is presented. Active diodes realized by MOS transistors only are employed to prevent reverse charge transfer. The switching low dropout regulator consists of a dual-loop voltage follower that could drive a large switch-capacitive load and achieves a fast load transient of less than 5mus for a 140mA current step. The regulated doubler was fabricated in a 0.35mum CMOS process occupying an area of 0.74mm2","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"24 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126000102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Low-Power Receiver with Switched-Capacitor Summation DFE 具有开关电容求和DFE的低功耗接收机
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705375
A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C. Yang, D. Friedman
{"title":"A Low-Power Receiver with Switched-Capacitor Summation DFE","authors":"A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C. Yang, D. Friedman","doi":"10.1109/VLSIC.2006.1705375","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705375","url":null,"abstract":"A low power receiver with a one tap DFE was fabricated in 90nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130747234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 46% Efficient 0.8dBm Transmitter for Wireless Sensor Networks 用于无线传感器网络的46%效率0.8dBm发射机
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705303
Y. Chee, A. Niknejad, J. Rabaey
{"title":"A 46% Efficient 0.8dBm Transmitter for Wireless Sensor Networks","authors":"Y. Chee, A. Niknejad, J. Rabaey","doi":"10.1109/VLSIC.2006.1705303","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705303","url":null,"abstract":"This paper presents a 1.9GHz low power transmitter for wireless sensor networks. It uses film bulk acoustic resonators (FBAR) for RF carrier generation and is co-designed with the antenna. The two-channel transmitter is 46% efficient when radiating 1.2mW from a 650mV supply. With 50% on-off keying, it consumes 1.35mW and supports data rate up till 330kbps. The 1.2times0.8mm2 transmitter is implemented in 0.13mum CMOS and is integrated into a 38times25times8.5mm3 solar powered sensor node","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131724391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
A Wide Tracking Range 0.2-4Gbps Clock and Data Recovery Circuit 宽跟踪范围0.2-4Gbps时钟和数据恢复电路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705317
P. Hanumolu, Gu-Yeon Wei, U. Moon
{"title":"A Wide Tracking Range 0.2-4Gbps Clock and Data Recovery Circuit","authors":"P. Hanumolu, Gu-Yeon Wei, U. Moon","doi":"10.1109/VLSIC.2006.1705317","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705317","url":null,"abstract":"A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18mum CMOS process achieves BER < 10-12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Finger Vein Authentication Technology and Its Future 手指静脉认证技术及其未来
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705285
Junichi Hashimoto
{"title":"Finger Vein Authentication Technology and Its Future","authors":"Junichi Hashimoto","doi":"10.1109/VLSIC.2006.1705285","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705285","url":null,"abstract":"In this paper, finger vein authentication, a new biometric method utilizing the vein patterns inside one's fingers for personal identification, is introduced. Vein patterns are different for each finger and for each person, and as they are hidden underneath the skin's surface, forgery is extremely difficult. These unique aspects of finger vein pattern recognition set it apart from previous forms of biometrics and have led to its adoption by the major Japanese financial institutions as their newest security technology. This paper discusses the technology and applications of finger vein authentication, as well as the importance of semiconductor devices in its future development","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124160575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 198
A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency 2.60pJ/Inst亚阈值传感器处理器实现最佳能效
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705356
Bo Zhai, L. Nazhandali, Javin Olson, Anna Reeves, M. Minuth, Ryan Helfand, Sanjay Pant, D. Blaauw, T. Austin
{"title":"A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency","authors":"Bo Zhai, L. Nazhandali, Javin Olson, Anna Reeves, M. Minuth, Ryan Helfand, Sanjay Pant, D. Blaauw, T. Austin","doi":"10.1109/VLSIC.2006.1705356","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705356","url":null,"abstract":"A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency and optimal voltage and evaluate the need for adaptive control. The processor reaches maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at 833kHz. The minimum energy consumption of the core marks a 10times improvement over previous sensor processors at the same MIPS","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114510453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 225
A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell 基于虚拟单元多重平均方案的128Mb浮体内存(FBRAM)
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705369
T. Ohsawa, T. Higashi, K. Fujita, K. Hatsuda, N. Ikumi, T. Shino, H. Nakajima, Y. Minami, N. Kusunoki, A. Sakamoto, J. Nishimura, T. Hamamoto, S. Fujii
{"title":"A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell","authors":"T. Ohsawa, T. Higashi, K. Fujita, K. Hatsuda, N. Ikumi, T. Shino, H. Nakajima, Y. Minami, N. Kusunoki, A. Sakamoto, J. Nishimura, T. Hamamoto, S. Fujii","doi":"10.1109/VLSIC.2006.1705369","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705369","url":null,"abstract":"A 128Mbit FBRAM using the floating body cell (FBC) the size of 0.17mum<sup>2</sup> (6.24F<sup>2</sup> with F=0.165mum) was successfully fabricated and a high bit yield (~99.999%) was obtained","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114825964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 40-GHz Wide-Tuning-Range VCO in 0.18-~m CMOS 0.18 ~m CMOS中的40ghz宽调谐范围压控振荡器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705368
Jun-Chau Chien, Liang-Hung Lu
{"title":"A 40-GHz Wide-Tuning-Range VCO in 0.18-~m CMOS","authors":"Jun-Chau Chien, Liang-Hung Lu","doi":"10.1109/VLSIC.2006.1705368","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705368","url":null,"abstract":"A 40-GHz wideband VCO is demonstrated in a standard 0.18-mum CMOS technology. In order to achieve wide tuning range at millimeter-wave frequencies, a non-uniform standing-wave VCO with a switched-transmission line architecture is proposed. By switching the length of the transmission line, a frequency tuning range of 7.5 GHz is achieved for the 40-GHz VCO design while maintaining a phase noise better than -96 dBc/Hz at 1-MHz offset","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125916961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 3500fps High-Speed CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters 一个3500fps高速CMOS图像传感器与12b列-并行循环A/D转换器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705292
M. Furuta, T. Inoue, Y. Nishikawa, S. Kawahito
{"title":"A 3500fps High-Speed CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters","authors":"M. Furuta, T. Inoue, Y. Nishikawa, S. Kawahito","doi":"10.1109/VLSIC.2006.1705292","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705292","url":null,"abstract":"This paper presents a high-speed CMOS image sensor with a global electronic shutter and 12b column parallel cyclic A/D converters. The fabricated chip in 0.25mum CMOS imager technology achieves the full frame rate in excess of 3500 frames per second. The in-pixel charge amplifier achieves the optical sensitivity of 19.9V/lx middot s and the dynamic range of 60dB","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126229596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 184mW Fully Integrated DVB-H Tuner Chip with Distortion Compensated Variable Gain LNA 带失真补偿变增益LNA的184mW全集成DVB-H调谐器芯片
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705301
H. Kawamura, T. Fujiwara, K. Kagoshima, S. Kawama, H. Kijima, M. Koutani, S. Toyoyama, K. Sakuno, K. Iizuka
{"title":"A 184mW Fully Integrated DVB-H Tuner Chip with Distortion Compensated Variable Gain LNA","authors":"H. Kawamura, T. Fujiwara, K. Kagoshima, S. Kawama, H. Kijima, M. Koutani, S. Toyoyama, K. Sakuno, K. Iizuka","doi":"10.1109/VLSIC.2006.1705301","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705301","url":null,"abstract":"A single chip direct conversion DVB-H tuner with a distortion compensated variable gain LNA is implemented in 0.5mum SiGe BiCMOS. The LNA exhibits 0dBm IIP3 and 2.8dB NF at 860MHz. A new offset cancel feedback is introduced that keeps the cutoff frequency independent of the baseband gain. The IC consumes 184mW at 2.8V while achieving a sensitivity of -96dBm for QPSK, CR=1/2 signal","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121635956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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