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引用次数: 8
摘要
一种混合模拟和数字四分之一速率时钟和数据恢复电路采用带delta-sigma截断的二阶数字环路滤波器来实现sub-ps相位分辨率和优于2ppm频率分辨率。在0.18 μ m CMOS工艺中制造的测试芯片在2Gbps下实现了BER < 10-12，功耗为14mW。在10kHz和20kHz调制频率下，跟踪范围分别大于plusmn5000 ppm和plusmn2500 ppm，因此，使该CDR适用于扩频时钟系统
A Wide Tracking Range 0.2-4Gbps Clock and Data Recovery Circuit
A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18mum CMOS process achieves BER < 10-12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking
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