2.60pJ/Inst亚阈值传感器处理器实现最佳能效

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705356

Bo Zhai, L. Nazhandali, Javin Olson, Anna Reeves, M. Minuth, Ryan Helfand, Sanjay Pant, D. Blaauw, T. Austin

{"title":"2.60pJ/Inst亚阈值传感器处理器实现最佳能效","authors":"Bo Zhai, L. Nazhandali, Javin Olson, Anna Reeves, M. Minuth, Ryan Helfand, Sanjay Pant, D. Blaauw, T. Austin","doi":"10.1109/VLSIC.2006.1705356","DOIUrl":null,"url":null,"abstract":"A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency and optimal voltage and evaluate the need for adaptive control. The processor reaches maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at 833kHz. The minimum energy consumption of the core marks a 10times improvement over previous sensor processors at the same MIPS","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"225","resultStr":"{\"title\":\"A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency\",\"authors\":\"Bo Zhai, L. Nazhandali, Javin Olson, Anna Reeves, M. Minuth, Ryan Helfand, Sanjay Pant, D. Blaauw, T. Austin\",\"doi\":\"10.1109/VLSIC.2006.1705356\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency and optimal voltage and evaluate the need for adaptive control. The processor reaches maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at 833kHz. The minimum energy consumption of the core marks a 10times improvement over previous sensor processors at the same MIPS\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"225\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705356\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705356","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 225

摘要

研制了一种以能效为目标的2.6pJ/Inst亚阈值传感器处理器。实现了一种两阶段微体系结构，以减轻亚阈值操作过程变化的影响。仔细的库单元选择和强大的SRAM设计使1.2V至200mV的全功能运行。我们分析了频率和最优电压的变化，并评估了自适应控制的必要性。处理器在360mV时达到最大能量效率，在833kHz时消耗2.6pJ/Inst。核心的最低能耗标志着在相同MIPS下比以前的传感器处理器提高了10倍

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency

A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency and optimal voltage and evaluate the need for adaptive control. The processor reaches maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at 833kHz. The minimum energy consumption of the core marks a 10times improvement over previous sensor processors at the same MIPS

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

自引率

0.00%

发文量