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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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An 11-Band 3.4 to 10.3 GHz MB-OFDM UWB Receiver in 0.25/spl mu/m SiGe BiCMOS 一个11波段3.4至10.3 GHz MB-OFDM UWB接收机在0.25/spl mu/m SiGe BiCMOS
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705382
A. Valdes-Garcia, Chinmaya Mishra, F. Bahmani, J. Silva-Martínez, E. Sánchez-Sinencio
{"title":"An 11-Band 3.4 to 10.3 GHz MB-OFDM UWB Receiver in 0.25/spl mu/m SiGe BiCMOS","authors":"A. Valdes-Garcia, Chinmaya Mishra, F. Bahmani, J. Silva-Martínez, E. Sánchez-Sinencio","doi":"10.1109/VLSIC.2006.1705382","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705382","url":null,"abstract":"An 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB is implemented in a 0.25mum BiCMOS process. It includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The packaged IC mounted on FR-4 substrate provides maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130491236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 500MS/s 5b ADC in 65nm CMOS 采用65nm CMOS的500MS/s 5b ADC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705349
B. Ginsburg, A. Chandrakasan
{"title":"A 500MS/s 5b ADC in 65nm CMOS","authors":"B. Ginsburg, A. Chandrakasan","doi":"10.1109/VLSIC.2006.1705349","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705349","url":null,"abstract":"A 1.2V 6mW 500MS/s 5-bit ADC for use in a UWB receiver has been fabricated in a pure digital 65nm CMOS technology. The ADC uses a 6-channel time-interleaved successive approximation register architecture. Each of the channels has a split capacitor array to reduce switching energy and sensitivity to digital timing skew. A variable delay line is used to optimize the instant of latch strobing to reduce preamplifier currents","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115128447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage 基于65nm和45nm技术节点的SRAM设计，具有扩展工作电压的读写辅助电路
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705289
H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, F. Towler
{"title":"An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage","authors":"H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, F. Towler","doi":"10.1109/VLSIC.2006.1705289","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705289","url":null,"abstract":"This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131042815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 113
A Single-Tank Dual-Band Reconfigurable Oscillator 单槽双波段可重构振荡器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705367
R. Gharpurey, Tien-Ling Hsieh, S. Venkatraman
{"title":"A Single-Tank Dual-Band Reconfigurable Oscillator","authors":"R. Gharpurey, Tien-Ling Hsieh, S. Venkatraman","doi":"10.1109/VLSIC.2006.1705367","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705367","url":null,"abstract":"An area-efficient oscillator topology for dual-band application is presented. The oscillator can be configured to operate in one of two states with distinct oscillation frequencies by reconfiguration of negative transconductance cores that excite the oscillator tank. The oscillator operates at nominal bands of 2.9 GHz and 6.5 GHz. Phase noise performance is presented for both bands. The oscillator is implemented in a 90nm digital CMOS process","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131191217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A SRAM Core Architecture with Adaptive Cell Bias Scheme 一种具有自适应单元偏置方案的SRAM核心结构
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705343
Hak-soo Yu, Nam-Seog Kim, Young-Jae Son, Yong-geol Kim, Hyo-Chang Kim, Uk-Rae Cho, H. Byun
{"title":"A SRAM Core Architecture with Adaptive Cell Bias Scheme","authors":"Hak-soo Yu, Nam-Seog Kim, Young-Jae Son, Yong-geol Kim, Hyo-Chang Kim, Uk-Rae Cho, H. Byun","doi":"10.1109/VLSIC.2006.1705343","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705343","url":null,"abstract":"This paper describes an adaptive cell bias scheme that is proposed to achieve high performance and stability for a low power, high speed, and high density SRAM core with less process variation. The proposed scheme is featured with constrained-successive cell bias optimization method that determines the optimal cell bias condition sequentially to meet both the speed and stability target of a given SRAM core. The architecture with adaptive cell bias scheme is applied to a 144Mb double stacked S3 SRAM and leads to 49% reduction in SRAM core performance parameter variations with 8% area overhead. The power reduction is 21%","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134599368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 35-Gb/s Limiting Amplifier in 0.13/spl mu/m CMOS Technology 基于0.13/spl mu/m CMOS技术的35 gb /s限幅放大器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705340
Chihun Lee, Shen-Iuan Liu
{"title":"A 35-Gb/s Limiting Amplifier in 0.13/spl mu/m CMOS Technology","authors":"Chihun Lee, Shen-Iuan Liu","doi":"10.1109/VLSIC.2006.1705340","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705340","url":null,"abstract":"A 35Gb/s limiting amplifier using cascaded-distributed amplifiers with active feedback and on-chip transformers achieves a differential gain SDD21 of 38 dB and a bandwidth of 26.2GHz. It has been fabricated in 0.13mum CMOS technology. It exhibits a single-ended output swing of 300mVPP while consuming 125mW from a 1.5V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130743958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering 15b线性，20MS/s, 1.5b/级流水线ADC数字校准与信号相关的抖动
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705388
Yun-Shiang Shu, B. Song
{"title":"A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering","authors":"Yun-Shiang Shu, B. Song","doi":"10.1109/VLSIC.2006.1705388","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705388","url":null,"abstract":"A signal-dependent dithering concept is developed to measure the multiplying DAC (MDAC) gain error of a 1.5b/stage pipelined ADC in background. A 15b, 20MS/s prototype ADC exhibits SFDR and THD of 98 and -92dB with 14.5MHz input. The chip fabricated in 0.18mum CMOS occupies 2.3 times 1.7mm2, and consumes 285mW at 1.8V","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116305717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
0.9-V Rail-to-Rail Operational Amplifiers with Adaptive Threshold Voltage Control 具有自适应阈值电压控制的0.9 v轨对轨运算放大器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705325
T. Adachi, K. Takasuka
{"title":"0.9-V Rail-to-Rail Operational Amplifiers with Adaptive Threshold Voltage Control","authors":"T. Adachi, K. Takasuka","doi":"10.1109/VLSIC.2006.1705325","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705325","url":null,"abstract":"Rail-to-rail operational amplifiers with an adaptive threshold voltage control circuit are designed at low supply voltage of 0.9-V. The control circuit using a bulk bias effect acts to keep enough drain-source voltage for the current source transistor connected with sources of the input transistors. Two types of operational amplifier based on the adaptive threshold voltage control technique are developed for 0.9-V supply voltage, and fabricated in a 0.35-mum CMOS process. Experimental results show that the developed control circuits improve input common-mode voltage range","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"44 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128429205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.3mW Baseband Impulse-UWB Transceiver Front-End in CMOS 基于CMOS的2.3mW基带脉冲超宽带收发器前端
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705379
Ian D O 'donnell, R. Brodersen, Clk Gen
{"title":"A 2.3mW Baseband Impulse-UWB Transceiver Front-End in CMOS","authors":"Ian D O 'donnell, R. Brodersen, Clk Gen","doi":"10.1109/VLSIC.2006.1705379","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705379","url":null,"abstract":"A highly integrated, flexible, baseband impulse-UWB transceiver front-end has been implemented in a standard 0.13mum CMOS process with power consumption of 1.8mW (RX) and 0.5mW (TX) at 10 Mpulses/s with a 1.1V supply. This transceiver targets a sensor network application and comprises a 1-bit, 1.92 GSample/s A/D conversion, 50Omega input matching with 0dB-42dB variable gain, control logic, 60MHz oscillator, and a pulse transmitter. Pulse transmission and reception are demonstrated","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133675640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment 一种最小工作电压为0.3 v的高容量SRAM
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705288
Y. Morita, H. Fujiwara, Hiroki Noguchi, K. Kawakami, J. Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, M. Yoshimoto
{"title":"A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment","authors":"Y. Morita, H. Fujiwara, Hiroki Noguchi, K. Kawakami, J. Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/VLSIC.2006.1705288","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705288","url":null,"abstract":"This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable operation in a wide range of Vdd under DVS environment. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that 30% power reduction is achieved at 100 MHz. The area overhead is only 5.6%","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124163579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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