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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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A Novel Program and Read Architecture for Contact-Less Virtual Ground NOR Flash Memory for High Density Application 一种新型高密度非接触式虚拟地NOR闪存的程序和读取结构
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705337
N. Ito, Y. Yamauchi, N. Ueda, K. Yamamoto, Y. Sugita, T. Mineyama, A. Ishihama, K. Moritani
{"title":"A Novel Program and Read Architecture for Contact-Less Virtual Ground NOR Flash Memory for High Density Application","authors":"N. Ito, Y. Yamauchi, N. Ueda, K. Yamamoto, Y. Sugita, T. Mineyama, A. Ishihama, K. Moritani","doi":"10.1109/VLSIC.2006.1705337","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705337","url":null,"abstract":"We have successfully developed multilevel (MLC) contact-less virtual ground array (VGA-NOR) flash memory. Sequential program from the source side edge cell of each segment and 32cells unit program with data buffer enable to cancel the Vt interference. Sense amplifier (SA) assist equalize-sensing (SAES) is implemented for high accuracy sensing operation","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129166328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories 随机电报信号对多电平闪存缩放的影响
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705335
H. Kurata, K. Otsuga, A. Kotabe, Shinya Kajiyama, T. Osabe, Y. Sasago, S. Narumi, K. Tokami, S. Kamohara, O. Tsuchiya
{"title":"The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories","authors":"H. Kurata, K. Otsuga, A. Kotabe, Shinya Kajiyama, T. Osabe, Y. Sasago, S. Narumi, K. Tokami, S. Kamohara, O. Tsuchiya","doi":"10.1109/VLSIC.2006.1705335","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705335","url":null,"abstract":"This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127596147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 125
Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory 自修复SRAM以减少奈米记忆体参数失效
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705345
S. Mukhopadhyay, Keejong Kim, H. Mahmoodi, A. Datta, Dongkyu Park, K. Roy
{"title":"Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory","authors":"S. Mukhopadhyay, Keejong Kim, H. Mahmoodi, A. Datta, Dongkyu Park, K. Roy","doi":"10.1109/VLSIC.2006.1705345","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705345","url":null,"abstract":"We present a self-repairing SRAM to reduce parametric failures using an on-chip leakage sensor and application of proper body bias. Simulations in a predictive 70nm technology show 5-40% (depending on inter-die Vt variation) improvement in SRAM yield. A test-chip is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the self-repair system","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130993367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter 一种亚皮秒分辨率0.5-1.5GHz数相转换器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705319
P. Hanumolu, V. Kratyuk, Gu-Yeon Wei, U. Moon
{"title":"A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter","authors":"P. Hanumolu, V. Kratyuk, Gu-Yeon Wei, U. Moon","doi":"10.1109/VLSIC.2006.1705319","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705319","url":null,"abstract":"A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122621710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques 采用电容耦合技术的1V 30mW 10b 100MSample/s管路A/D转换器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705391
K. Honda, F. Masanori, S. Kawahito
{"title":"A 1V 30mW 10b 100MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques","authors":"K. Honda, F. Masanori, S. Kawahito","doi":"10.1109/VLSIC.2006.1705391","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705391","url":null,"abstract":"A 10b 100MSample/s pipeline A/D converter in 90nm process consumes 30mW at 1.0V power supply. The proposed capacitance coupling S/H stage and capacitance coupled class-AB amplifier achieve low distortion and low power dissipation at high-speed sampling. The SNDR and SFDR at 100MHz sampling are 54.0 dB and 70.0 dB, respectively","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125367050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture 采用无负载架构的1 v 100MS/s 8位CMOS开关运放流水线ADC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705347
Ying Wu, V. Cheung, H. Luong
{"title":"A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture","authors":"Ying Wu, V. Cheung, H. Luong","doi":"10.1109/VLSIC.2006.1705347","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705347","url":null,"abstract":"A 1V, 8-bit dual-mode ADC is realized using multi-phase switched-opamp (SO) technique. Employing a proposed loading-free pipelined ADC architecture and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100MS/s conversion rate, which is the fastest operation speed reported at 1-V supply, and comparable to many high-voltage switched-capacitor (SC) ADC. Implemented in a 0.18mum CMOS process, the ADC obtains a peak SNR of 45dB and SFDR of 52.6dB while dissipating only 30mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124607133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A Cartesian-Feedback Linearized CMOS RF Transmitter for EDGE Modulation 一种用于边缘调制的直角反馈线性化CMOS射频发射机
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705395
L. Tee, E. Sacchi, R. Bocock, N. Wongkomet, P. Gray
{"title":"A Cartesian-Feedback Linearized CMOS RF Transmitter for EDGE Modulation","authors":"L. Tee, E. Sacchi, R. Bocock, N. Wongkomet, P. Gray","doi":"10.1109/VLSIC.2006.1705395","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705395","url":null,"abstract":"A 1.55GHz CMOS RF transmitter with an integrated class-C power amplifier (PA) is described. The transmitter uses Cartesian feedback to meet EDGE linearity requirements and integrates a direct-conversion modulator, PA, LO phase shifter, feedback mixers and baseband loop filter in a 0.18mum CMOS process. The transmitter produces an 18dBm EDGE modulated output with 18% drain efficiency","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116427939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology 采用部分沟槽隔离ABC SOI (PTI-ABC SOI)的低功耗SOC设计用于sub - 100nm LSTP技术
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705372
O. Ozawa, K. Fukuoka, Y. Igarashi, T. Kuraishi, Y. Yasu, Y. Maki, T. Ipposhi, T. Ochiai, M. Shirahata, K. Ishibashi
{"title":"Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology","authors":"O. Ozawa, K. Fukuoka, Y. Igarashi, T. Kuraishi, Y. Yasu, Y. Maki, T. Ipposhi, T. Ochiai, M. Shirahata, K. Ishibashi","doi":"10.1109/VLSIC.2006.1705372","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705372","url":null,"abstract":"The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125826456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of 90nm 1Gb ORNAND/sup TM/ Flash Memory with MirrorBit/sup TM/ Technology 采用MirrorBit/sup TM/ Technology的90nm 1Gb ORNAND/sup TM/闪存设计
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705336
T. Kuo, N. Yang, N. Leong, E. Wang, F. Lai, A. Lee, H. Chen, S. Chandra, Y. Wu, T. Akaogi, A. Melik-Martirosian, A. Pourkeramati, J. Thomas, M. Vanbuskirk
{"title":"Design of 90nm 1Gb ORNAND/sup TM/ Flash Memory with MirrorBit/sup TM/ Technology","authors":"T. Kuo, N. Yang, N. Leong, E. Wang, F. Lai, A. Lee, H. Chen, S. Chandra, Y. Wu, T. Akaogi, A. Melik-Martirosian, A. Pourkeramati, J. Thomas, M. Vanbuskirk","doi":"10.1109/VLSIC.2006.1705336","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705336","url":null,"abstract":"Using the virtual ground array structure of 2 bits/cell MirrorBittrade technology, a 90nm, 1.8V ORNANDtrade product combining the advantages of both NOR and NAND is presented. Full NAND functionality and performance compatibility is shown, while maintaining the NOR advantages","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132177971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A test structure for characterizing local device mismatches 一种用于表征本地设备不匹配的测试结构
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705315
K. Agarwal, Frank Liu, C. McDowell, S. Nassif, K. Nowka, Meghann Palmer, D. Acharyya, J. Plusquellic
{"title":"A test structure for characterizing local device mismatches","authors":"K. Agarwal, Frank Liu, C. McDowell, S. Nassif, K. Nowka, Meghann Palmer, D. Acharyya, J. Plusquellic","doi":"10.1109/VLSIC.2006.1705315","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705315","url":null,"abstract":"We present a test structure for statistical characterization of local device mismatches. The structure contains densely populated SRAM devices arranged in an addressable manner. Measurements on a test chip fabricated in an advanced 65 nm process show little spatial correlation. We vary the nominal threshold voltage of the devices by changing the threshold-adjust implantations and observe that the ratio of standard deviation to mean gets worse with threshold scaling. The large variations observed in the extracted threshold voltage statistics indicate that the random doping fluctuation is the likely reason behind mismatch in the adjacent devices","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
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