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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter 一种带新型三相开关电容环滤波器的超宽范围数字自适应控制锁相环
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1093/ietele/e90-c.6.1197
S. Dosho, N. Yanagisawa, Kazuaki Sogawa, Y. Yamada, T. Morie
{"title":"An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter","authors":"S. Dosho, N. Yanagisawa, Kazuaki Sogawa, Y. Yamada, T. Morie","doi":"10.1093/ietele/e90-c.6.1197","DOIUrl":"https://doi.org/10.1093/ietele/e90-c.6.1197","url":null,"abstract":"Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. Recently, the widest span of the input frequency has reached 640 times. Although the large divider ratio of the feedback divider relaxes the variation by lowering the VCO gain, the variation of the charge pump current reaches 6400 times in using conventional methods. The new method moderates the variation by changing the gain of the VCO and the capacitance of the loop filter in addition to the charge pump current. Loop filters in the PLL have been evolving along with the improvement of adaptive-biased PLLs. Switched capacitor type loop filters (SC-LPFs) are tolerable to wide variation of the cutoff frequency and preferable for reducing the pattern jitter which appears remarkably on the PLL with high divider ratio. However, the conventional SC-LPF is slightly complex. Thus, the simple 3-phase SC-LPF which realizes the fully flat response has been developed","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133084607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-Performance Processors in a Power-Limited World 功率有限世界中的高性能处理器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705327
S. Naffziger
{"title":"High-Performance Processors in a Power-Limited World","authors":"S. Naffziger","doi":"10.1109/VLSIC.2006.1705327","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705327","url":null,"abstract":"Processor designers and the VLSI industry in general have truly hit the power wall. Many options have been and are being explored to mitigate or circumvent the impact of power limits on performance, but all of these solutions have limited effect and application. The implications of this fundamental limit are far reaching for processor architectures and the shape of computing in coming years. This paper explores the nature of power limitations and some of the implications for the future of processor design","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123450387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time 具有门控二极管的3晶体管DRAM单元，可提高速度和保持时间
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705371
W. Luk, Jin Cai, R. Dennard, M. Immediato, S. Kosonocky
{"title":"A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time","authors":"W. Luk, Jin Cai, R. Dennard, M. Immediato, S. Kosonocky","doi":"10.1109/VLSIC.2006.1705371","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705371","url":null,"abstract":"3T1D is a non-destructive read DRAM cell with three transistors (T) and a gated diode (D). The gated diode acts as a storage device and an amplifier, leading to low voltage, high speed and high tolerance to variability, and comparing favorably to conventional 3T gain cell and 6T SRAM cell. Hardware measurements in 90 nm SOI showed the 3T1D achieved longer retention than the 3T. Retention, speed and scaling perspectives for future technology are presented","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
A Power-Managed Protocol Processor for Wireless Sensor Networks 无线传感器网络的电源管理协议处理器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705385
M. Sheets, F. Burghardt, T. Karalar, J. Ammer, Y. Chee, J. Rabaey
{"title":"A Power-Managed Protocol Processor for Wireless Sensor Networks","authors":"M. Sheets, F. Burghardt, T. Karalar, J. Ammer, Y. Chee, J. Rabaey","doi":"10.1109/VLSIC.2006.1705385","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705385","url":null,"abstract":"Wireless sensor network applications, such as environmental control in smart building and ecological monitoring, require low-power nodes that operate their entire lifetime without changing batteries. This paper describes the power management architecture for a digital protocol processor for a sensor network node. Eight subsystems implement the baseband through application protocol layers and are controlled by a centralized power manager. The prototype chip, implemented in 130nm CMOS, operates at 1.0V with an average power consumption of 150muW during normal operation","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123534529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
A Non-Volatile 2Mbit CBRAM Memory Core Featuring Advanced Read and Program Control 一个非易失性2Mbit CBRAM存储器核心具有先进的读取和程序控制
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705334
H. Honigschmid, M. Angerbauer, S. Dietrich, M. Dimitrova, D. Gogl, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, G. Muller
{"title":"A Non-Volatile 2Mbit CBRAM Memory Core Featuring Advanced Read and Program Control","authors":"H. Honigschmid, M. Angerbauer, S. Dietrich, M. Dimitrova, D. Gogl, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, G. Muller","doi":"10.1109/VLSIC.2006.1705334","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705334","url":null,"abstract":"A 2Mbit CBRAM (conductive bridging random access memory) core has been developed utilizing a 90nm, VDD = 1.5V process technology. The presented design uses an 8F2 (0.0648mum2) 1T1CBJ (1-transistor/1-conductive bridging junction) cell and introduces a fast feedback regulated CBJ read voltage and a novel program charge control using dummy cell bleeder devices. Random read/write cycle times les50ns are demonstrated","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling 31.2mW超宽带基带收发器，全数字I/ q错配校准和动态采样
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705397
J. Yu, Ching-Che Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, Chen-Yi Lee
{"title":"A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling","authors":"J. Yu, Ching-Che Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, Chen-Yi Lee","doi":"10.1109/VLSIC.2006.1705397","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705397","url":null,"abstract":"A MB-OFDM UWB baseband transceiver with I/Q-mismatch (IQM) calibration and dynamic sampling (DS) is presented. It calibrates IQM by 2dB gain and 20 degree phase errors, releasing IQM tolerance to 10times of existing designs. The DS reduces ADC sampling rate to 1/9 ~ frac12 of existing designs, resulting in at least 43% ADC power saving. Measured power consumes 31.2mW at 480Mb/s data rate","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125120512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme 使用混合平均方案的7位800Msps 120mW折叠和插值ADC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705348
K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, M. Segami
{"title":"A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme","authors":"K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, M. Segami","doi":"10.1109/VLSIC.2006.1705348","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705348","url":null,"abstract":"A 7bit 800Msps folding and interpolation ADC is presented. This ADC uses new offset-averaging schemes in preamplifiers and current-mode interpolation stages and a digital-averaging scheme in a comparator stage to operate at higher speed with low power dissipation. The measured SNR is 36.8dB at a 200MHz input frequency. The prototype of the complete ADC is fabricated in a 90nm digital CMOS process and consumes 120mW with 2.5V and 1.2V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127404855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
The Past, Present, and Future of Data Converters and Mixed Signal ICs: A "Universal" Model 数据转换器和混合信号集成电路的过去、现在和未来:一个“通用”模型
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705284
D. Robertson
{"title":"The Past, Present, and Future of Data Converters and Mixed Signal ICs: A \"Universal\" Model","authors":"D. Robertson","doi":"10.1109/VLSIC.2006.1705284","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705284","url":null,"abstract":"In both technology and business circles, much attention is paid to the trends in the electronics and semiconductor industry. It is frequently noted that the \"world is going digital\"-with the implication that analog circuits and data converters will ultimately be relegated to a support role for enormous digital VLSI \"masters\". This paper considers a number of different models for development from different fields of science, looking for possible insights or implications for the future of mixed signal processing. It then considers a brief history of converter development, and emerging data converter trends, looking for clues to the future of data converters and mixed signal ICs","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114894733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Single Chip 2.5 Gbps CMOS Burst Mode Optical Receiver 单片2.5 Gbps CMOS突发模式光接收机
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705339
Wei-Zen Chen, Ruei-Ming Gan
{"title":"A Single Chip 2.5 Gbps CMOS Burst Mode Optical Receiver","authors":"Wei-Zen Chen, Ruei-Ming Gan","doi":"10.1109/VLSIC.2006.1705339","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705339","url":null,"abstract":"This paper describes the design of a 2.5 Gbps burst-mode optical receiver in a 0.18 mum CMOS process. Integrating both transimpedance amplifier and post limiting amplifier in a single chip, the input sensitivity of the optical receiver is about -18 dBm, and the response time is less than 50 ns. The overall transimpedance gain is 98 dBOmega, and the -3 dB bandwidth is about 1.85 GHz. Operating under a single 1.8 V supply, this chip dissipates only 122 mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121941812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 4GHz 4th-Order Passive LC Bandpass Delta-Sigma Modulator with IF at 1.4GHz 中频为1.4GHz的4GHz四阶无源LC带通δ - σ调制器
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705363
L. Luh, J. Jensen, Cheng-Min Lin, Chan-Tang Tsen, D. Le, A. Cosand, S. Thomas, C. Fields
{"title":"A 4GHz 4th-Order Passive LC Bandpass Delta-Sigma Modulator with IF at 1.4GHz","authors":"L. Luh, J. Jensen, Cheng-Min Lin, Chan-Tang Tsen, D. Le, A. Cosand, S. Thomas, C. Fields","doi":"10.1109/VLSIC.2006.1705363","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705363","url":null,"abstract":"A 4th-order bandpass DeltaSigma modulator utilizes a novel passive LC continuous-time DeltaSigma architecture to achieve the high IF (pass band) frequency (1.4GHz). A 3-bit quantizer is used to improve wideband performance. A novel architecture of noise-shaped quantizer is used to noise shape the DAC mismatch without introducing extra loop delay. Eight 2nd-order LC modulators are used for noise shaping with minimal transistor count and power consumption. Implemented with 5195 InP HBT transistors, this modulator achieved 76dB SNR and 90dB dynamic range in 1 MHz bandwidth at 1.4GHz with a 4GHz sample rate","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129783509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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