{"title":"A Single Chip 2.5 Gbps CMOS Burst Mode Optical Receiver","authors":"Wei-Zen Chen, Ruei-Ming Gan","doi":"10.1109/VLSIC.2006.1705339","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a 2.5 Gbps burst-mode optical receiver in a 0.18 mum CMOS process. Integrating both transimpedance amplifier and post limiting amplifier in a single chip, the input sensitivity of the optical receiver is about -18 dBm, and the response time is less than 50 ns. The overall transimpedance gain is 98 dBOmega, and the -3 dB bandwidth is about 1.85 GHz. Operating under a single 1.8 V supply, this chip dissipates only 122 mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705339","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper describes the design of a 2.5 Gbps burst-mode optical receiver in a 0.18 mum CMOS process. Integrating both transimpedance amplifier and post limiting amplifier in a single chip, the input sensitivity of the optical receiver is about -18 dBm, and the response time is less than 50 ns. The overall transimpedance gain is 98 dBOmega, and the -3 dB bandwidth is about 1.85 GHz. Operating under a single 1.8 V supply, this chip dissipates only 122 mW