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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.最新文献

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A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip 基于时钟门控的65nm数字基带调制解调器芯片泄漏管理系统
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705386
F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko
{"title":"A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip","authors":"F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko","doi":"10.1109/VLSIC.2006.1705386","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705386","url":null,"abstract":"In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129441702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
17GHz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator 等幅驻波振荡器的17GHz精细网格时钟分布
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705328
M. Sasaki, M. Shiozaki, A. Mori, A. Iwata, H. Ikeda
{"title":"17GHz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator","authors":"M. Sasaki, M. Shiozaki, A. Mori, A. Iwata, H. Ikeda","doi":"10.1109/VLSIC.2006.1705328","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705328","url":null,"abstract":"This paper presents an inductive-loaded standing-wave clock oscillator. By coupling the oscillators into mesh structure, multi-ten GHz uniform-phase/amplitude global clocks can be distributed over a whole chip. In the mesh structure, finer grid can be employed than the conventional standing-wave technique, and it makes the depth of clock tree very shallow. We designed and fabricated a 17.2GHz oscillator in a 0.18mum 6 metal CMOS technology. Low jitter less than 0.2% of the clock period has been achieved with 400mum transmission line that was less than 1/10 of the conventional one. The power consumption was 13mW at 1.8V supply voltage","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter 用于0.125-2Gbps 0.18/spl mu/m CMOS发射机的多相锁相环
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705299
Yongsam Moon, Daeyun Shim
{"title":"A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter","authors":"Yongsam Moon, Daeyun Shim","doi":"10.1109/VLSIC.2006.1705299","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705299","url":null,"abstract":"A 0.18-mum CMOS DLL generates equally-spaced multiphase clocks over 16times range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32times lock range, which is at least 3.5times wider comparing with conventional multiphase DLL's. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129951440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MRAM Cell Technology for Over 500MHz SoC 超过500MHz SoC的MRAM单元技术
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705333
N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, S. Tahara
{"title":"MRAM Cell Technology for Over 500MHz SoC","authors":"N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, S. Tahara","doi":"10.1109/VLSIC.2006.1705333","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705333","url":null,"abstract":"We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under 1ns is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133276094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.9-V 96-/spl mu/W Digital Hearing Aid Chip with Heterogeneous S-D DAC 带有异构S-D DAC的0.9 v 96 /spl mu/W数字助听器芯片
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705309
Sunyoung Kim, Namjun Cho, Seong-Jun Song, Donghyun Kim, Kwanho Kim
{"title":"A 0.9-V 96-/spl mu/W Digital Hearing Aid Chip with Heterogeneous S-D DAC","authors":"Sunyoung Kim, Namjun Cho, Seong-Jun Song, Donghyun Kim, Kwanho Kim","doi":"10.1109/VLSIC.2006.1705309","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705309","url":null,"abstract":"A full chip implementation of a low-power digital hearing aid is reported. It is composed of preamplifier, Sigma-Delta ADC, DSP and Sigma-Delta DAC with low-power technique. The hardwired DSP has 6 parameters to reduce power consumption with high flexibility. The Sigma-Delta DAC adopts heterogeneous frequency to reduce power consumption further. The proposed digital hearing aid chip achieves 79-dB peak SNR and dissipates 96-muW from a single 0.9-V supply. The core area is 2.7-mm2 in a 0.18-mum standard CMOS technology","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":" 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132012273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link 用于20Gb/s链路的低抖动锁相环无中继时钟分配网络
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705296
F. O’Mahony, M. Mansuri, B. Casper, J. Jaussi, R. Mooney
{"title":"A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link","authors":"F. O’Mahony, M. Mansuri, B. Casper, J. Jaussi, R. Mooney","doi":"10.1109/VLSIC.2006.1705296","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705296","url":null,"abstract":"A 10GHz clock generation and distribution network for an 8-channel 20Gb/s/channel data transmitter is demonstrated in a 90nm 1.2V CMOS process. Jitter due to power supply and device noise is minimized with an LC VCO and repeaterless clock network. The performance of the forwarded-clock link degrades by only 4% due to plusmn5% supply noise at the transmitter. The LC VCO achieves supply noise sensitivity of 200MHz/V (0.02%-frequency/1%-supply noise) and short-term (8-symbol) rms jitter of 100fs. The clock distribution network delay sensitivity to supply noise is 36ps/V. The total clocking power is 408mW","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126722896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Impact of Layout on 90nm CMOS Process Parameter Fluctuations 布局对90nm CMOS工艺参数波动的影响
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705316
L. Pang, B. Nikolić
{"title":"Impact of Layout on 90nm CMOS Process Parameter Fluctuations","authors":"L. Pang, B. Nikolić","doi":"10.1109/VLSIC.2006.1705316","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705316","url":null,"abstract":"A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115925855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers 用于802.11a/b/g接收器的1V 14mw / channel Flexible-IF CMOS模拟基带IC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705396
Pui-in Mak, S. U, R. Martins
{"title":"A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers","authors":"Pui-in Mak, S. U, R. Martins","doi":"10.1109/VLSIC.2006.1705396","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705396","url":null,"abstract":"Presented is a low-voltage low-power analog-baseband IC featuring a two-step channel-selection architecture for a flexible-IF reception of 802.11a/b/g. In circuits, it integrates innovatively series-switching mixers for a precise I/Q demodulation; an inside-opamp dc-offset cancellation for area savings and switchability, a switched-current-resistor programmable-gain amplifier for a transient-free constant-bandwidth gain adjustment. Fabricated in a 0.35mum CMOS process, each channel consumes 14mW from 1V, while measuring <1mus gain-switched transient, 32/90dB stopband rejection at 20/40MHz and 15.2dBm IIP3","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 12b 10MS/s Pipelined ADC Using Reference Scaling 使用参考缩放的12b 10MS/s流水线ADC
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705389
G. Ahn, P. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita, K. Takasuka, G. Temes, U. Moon
{"title":"A 12b 10MS/s Pipelined ADC Using Reference Scaling","authors":"G. Ahn, P. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita, K. Takasuka, G. Temes, U. Moon","doi":"10.1109/VLSIC.2006.1705389","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705389","url":null,"abstract":"A 12b 10MS/s pipelined ADC using reference scaling achieves 62 dB SNDR and 72 dB SFDR for a 1MHz input. The prototype IC fabricated in a 0.35mum CMOS process employs interstage amplifiers with 45dB open-loop gain and consumes 19mW from a 2.4V supply","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128534637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Configurable Enhanced T/sup 2/RAM Macro for System-Level Power Management Unified Memory 用于系统级电源管理统一存储器的可配置增强T/sup 2/RAM宏
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI: 10.1109/VLSIC.2006.1705370
K. Arimoto, F. Morishita, I. Hayashi, I. Gyohten, H. Noda, T. Ipposhi, K. Dosaka
{"title":"A Configurable Enhanced T/sup 2/RAM Macro for System-Level Power Management Unified Memory","authors":"K. Arimoto, F. Morishita, I. Hayashi, I. Gyohten, H. Noda, T. Ipposhi, K. Dosaka","doi":"10.1109/VLSIC.2006.1705370","DOIUrl":"https://doi.org/10.1109/VLSIC.2006.1705370","url":null,"abstract":"TTRAM can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. The enhanced TTRAM (ET2RAM) can solve these issues and the key technologies provide 0.5V memory operation, compact and higher sensitivity sense amplifier, and programmable multi-bank array","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125940141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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