布局对90nm CMOS工艺参数波动的影响

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705316

L. Pang, B. Nikolić

{"title":"布局对90nm CMOS工艺参数波动的影响","authors":"L. Pang, B. Nikolić","doi":"10.1109/VLSIC.2006.1705316","DOIUrl":null,"url":null,"abstract":"A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"76","resultStr":"{\"title\":\"Impact of Layout on 90nm CMOS Process Parameter Fluctuations\",\"authors\":\"L. Pang, B. Nikolić\",\"doi\":\"10.1109/VLSIC.2006.1705316\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"76\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705316\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705316","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 76

摘要

建立了一种测试芯片，研究了90nm CMOS电路布局对数字电路延时和漏损的影响。延迟是通过环形振荡器频率的扩散来表征的，晶体管泄漏是通过片上ADC来测量的

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Impact of Layout on 90nm CMOS Process Parameter Fluctuations

A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC

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来源期刊

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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