F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko
{"title":"基于时钟门控的65nm数字基带调制解调器芯片泄漏管理系统","authors":"F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko","doi":"10.1109/VLSIC.2006.1705386","DOIUrl":null,"url":null,"abstract":"In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip\",\"authors\":\"F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko\",\"doi\":\"10.1109/VLSIC.2006.1705386\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705386\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705386","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip
In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
