{"title":"用于0.125-2Gbps 0.18/spl mu/m CMOS发射机的多相锁相环","authors":"Yongsam Moon, Daeyun Shim","doi":"10.1109/VLSIC.2006.1705299","DOIUrl":null,"url":null,"abstract":"A 0.18-mum CMOS DLL generates equally-spaced multiphase clocks over 16times range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32times lock range, which is at least 3.5times wider comparing with conventional multiphase DLL's. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps","PeriodicalId":366835,"journal":{"name":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter\",\"authors\":\"Yongsam Moon, Daeyun Shim\",\"doi\":\"10.1109/VLSIC.2006.1705299\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 0.18-mum CMOS DLL generates equally-spaced multiphase clocks over 16times range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32times lock range, which is at least 3.5times wider comparing with conventional multiphase DLL's. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps\",\"PeriodicalId\":366835,\"journal\":{\"name\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2006.1705299\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2006.1705299","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter
A 0.18-mum CMOS DLL generates equally-spaced multiphase clocks over 16times range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32times lock range, which is at least 3.5times wider comparing with conventional multiphase DLL's. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
