超过500MHz SoC的MRAM单元技术

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705333

N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, S. Tahara

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引用次数: 9

摘要

我们提出了两种新的MRAM细胞结构，2T1MTJ和5T2MTJ。虽然它们能够实现非常高速的运行，但它们需要小写电流的磁隧道结(MTJs)。我们发现，通过插入写线的新型MTJ，可以将写电流降低到1mA。5T2MTJ单元具有两个写电流开关和一个检测电路。仿真结果表明，当磁阻为5k-ohm，磁阻比(MR)为150%时，可实现小于1ns的访问时间

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MRAM Cell Technology for Over 500MHz SoC

We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under 1ns is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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