F. Jumel, P. Royannez, H. Mair, D. Scott, A. Er Rachidi, R. Lagerquist, M. Chau, S. Gururajarao, S. Thiruvengadam, M. Clinton, V. Menezes, R. Hollingsworth, J. Vaccani, F. Piacibello, N. Culp, J. Rosal, M. Ball, F. Ben-Amar, L. Bouetel, O. Domerego, J. Lachese, C. Fournet-Fayard, J. Ciroux, C. Raibaut, U. Ko
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引用次数: 9
Abstract
In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization
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