使用参考缩放的12b 10MS/s流水线ADC

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. Pub Date : 2006-06-15 DOI:10.1109/VLSIC.2006.1705389

G. Ahn, P. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita, K. Takasuka, G. Temes, U. Moon

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引用次数: 4

摘要

使用参考缩放的12b 10MS/s流水线ADC在1MHz输入时可实现62 dB SNDR和72 dB SFDR。原型IC采用0.35 μ m CMOS工艺制造，采用45dB开环增益的级间放大器，功耗为19mW，来自2.4V电源

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A 12b 10MS/s Pipelined ADC Using Reference Scaling

A 12b 10MS/s pipelined ADC using reference scaling achieves 62 dB SNDR and 72 dB SFDR for a 1MHz input. The prototype IC fabricated in a 0.35mum CMOS process employs interstage amplifiers with 45dB open-loop gain and consumes 19mW from a 2.4V supply

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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