An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

Abstract

Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. Recently, the widest span of the input frequency has reached 640 times. Although the large divider ratio of the feedback divider relaxes the variation by lowering the VCO gain, the variation of the charge pump current reaches 6400 times in using conventional methods. The new method moderates the variation by changing the gain of the VCO and the capacitance of the loop filter in addition to the charge pump current. Loop filters in the PLL have been evolving along with the improvement of adaptive-biased PLLs. Switched capacitor type loop filters (SC-LPFs) are tolerable to wide variation of the cutoff frequency and preferable for reducing the pattern jitter which appears remarkably on the PLL with high divider ratio. However, the conventional SC-LPF is slightly complex. Thus, the simple 3-phase SC-LPF which realizes the fully flat response has been developed