A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme

Abstract

A 7bit 800Msps folding and interpolation ADC is presented. This ADC uses new offset-averaging schemes in preamplifiers and current-mode interpolation stages and a digital-averaging scheme in a comparator stage to operate at higher speed with low power dissipation. The measured SNR is 36.8dB at a 200MHz input frequency. The prototype of the complete ADC is fabricated in a 90nm digital CMOS process and consumes 120mW with 2.5V and 1.2V supply