A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

Abstract

A 1V, 8-bit dual-mode ADC is realized using multi-phase switched-opamp (SO) technique. Employing a proposed loading-free pipelined ADC architecture and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100MS/s conversion rate, which is the fastest operation speed reported at 1-V supply, and comparable to many high-voltage switched-capacitor (SC) ADC. Implemented in a 0.18mum CMOS process, the ADC obtains a peak SNR of 45dB and SFDR of 52.6dB while dissipating only 30mW